RT54SX72S-CG624B datasheet, PDF

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RT54SX72S-CG624B: DescriptionField Programmable Gate Array, 4024 CLBs, 108000 Gates, 156MHz, 6036-Cell, CMOS, CPGA624, CERAMIC, CGA-624; CategoryProgrammable logic devices Programmable logic; File Size659KB，84 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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RT54SX72S-CG624B Overview

Field Programmable Gate Array, 4024 CLBs, 108000 Gates, 156MHz, 6036-Cell, CMOS, CPGA624, CERAMIC, CGA-624

RT54SX72S-CG624B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microsemi
package instruction	CGA, BGA624,25X25,50
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Other features	72000 TYPICAL GATES AVAILABLE
maximum clock frequency	156 MHz
Combined latency of CLB-Max	1.4 ns
JESD-30 code	S-CPGA-X624
length	32.5 mm
Configurable number of logic blocks	4024
Equivalent number of gates	108000
Number of entries	360
Number of logical units	6036
Output times	360
Number of terminals	624
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	4024 CLBS, 108000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	CGA
Encapsulate equivalent code	BGA624,25X25,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5,3.3/5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	MIL-STD-883 Class B
Maximum seat height	5.37 mm
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	UNSPECIFIED
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	32.5 mm

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v2 .2

™

RTSX-S RadTolerant FPGAs

Designed for Space

•

SEU-Hardened Registers Eliminate the Need to

Implement Triple-Module Redundancy (TMR)

– Immune to Single-Event Upsets (SEU) to LET

> 40 MeV-cm

/mg,

– SEU Rate < 10

–10

Upset/Bit-Day in Worst-Case

Geosynchronous Orbit

Up to 100 krad (Si) Total Ionizing Dose (TID)

– Parametric Performance Supported with Lot-

Specific Test Data

Single-Event Latch-Up (SEL) Immunity

TM1019.5 Test Data Available

QML Certified Devices

u e

Features

•

Very Low Power Consumption (Up to 68 mW at

Standby)

3.3V and 5V Mixed Voltage

Configurable I/O Support for 3.3V/5V PCI, LVTTL,

TTL, and CMOS

– 5V Input Tolerance and 5V Drive Strength

– Slow Slew Rate Option

– Configurable Weak Resistor Pull-Up/Down for

Tristated Outputs at Power-Up

– Hot-Swap

Compliant

with

Cold-Sparing

Support

Secure Programming Technology Prevents Reverse

Engineering and Design Theft

100% Circuit Resource Utilization with 100% Pin

Locking

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Low-Cost Prototyping Option

Deterministic, User-Controllable Timing

JTAG Boundary Scan Testing in Compliance with

IEEE Standard 1149.1 – Dedicated JTAG Reset

(TRST) Pin

•

High Performance

•

230 MHz System Performance

310 MHz Internal Performance

9.5 ns Input Clock to Output Pad

Specifications

•

0.25 µm Metal-to-Metal Antifuse Process

48,000 to 108,000 Available System Gates

Up to 2,012 SEU-Hardened Flip-Flops

Up to 360 User-Programmable I/O Pins

Table 1 •

RTSX-S Product Profile

Device

Capacity

Typical Gates

System Gates

Logic Modules

Combinatorial Cells

SEU-Hardened Register Cells (Dedicated Flip-Flops)

Maximum Flip-Flops

Maximum User I/Os

Clocks

Quadrant Clocks

Speed Grades

Package

(by pin count)

CQFP

CCGA

CCLG

RT54SX32S

32,000

48,000

2,880

1,800

1,080

1,980

227

Std., –1

208, 256

256

RT54SX72S

72,000

108,000

6,036

4,024

2,012

4,024

360

Std., –1

208, 256

624

November 2004

See Actel’s website for the latest version of the datasheet

RTSX-S RadTolerant FPGAs

Table of Contents

General Description

Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Low-Cost Prototyping Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Detailed Specification

General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

Package Pin Assignments

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

256-Pin CCLG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

624-Pin CCGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

v2.2

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