The UT54ACS245 and the UT54ACTS245 are non-inverting
octal bus transceivers designed for asynchronous two-way com-
munication between data buses. The control function imple-
mentation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic level
at the direction control (DIR) input. The enable input (G) dis-
ables the device so that the buses are effectively isolated.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
ENABLE
G
L
L
H
DIRECTION
CONTROL DIR
L
H
X
OPERATION
B Data To A Bus
A Data To B Bus
Isolation
PINOUTS
20-Pin DIP
Top View
DIR
A1
A2
A3
A4
A5
A6
A7
A8
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
G
B1
B2
B3
B4
B5
B6
B7
B8
20-Lead Flatpack
Top View
DIR
A1
A2
A3
A4
A5
A6
A7
A8
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
G
B1
B2
B3
B4
B5
B6
B7
B8
LOGIC SYMBOL
G
DIR
(19)
(1)
G3
3 EN1 (BA)
3 EN2 (AB)
(18)
1
2
(17)
(16)
(15)
(14)
B1
B2
B3
B4
A1
A2
A3
A4
A5
A6
A7
A8
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
B5
(13)
B6
(12)
B7
(11)
B8
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
165
RadHard MSI Logic
UT54ACS245/UT54ACTS245
LOGIC DIAGRAM
DIR
(1)
(19)
G
A1
(2)
(18)
B1
A2
(3)
(17)
B2
A3
(4)
(16)
B3
A4
(5)
(15)
B4
A5
(6)
(14)
B5
A6
(7)
(13)
B6
A7
(8)
(12)
B7
A8
(9)
(11)
B8
RadHard MSI Logic
166
UT54ACS245/UT54ACTS245
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
JC
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
10
1
UNITS
V
V
C
C
C
C/W
mA
W
I
I
P
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
C
167
RadHard MSI Logic
UT54ACS245/UT54ACTS245
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V 10%; V
SS
= 0V
6
, -55 C < T
C
< +125 C)
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Three-state output leakage current
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
I
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 12.0mA
I
OL
= 100 A
I
OH
= -12.0mA
I
OH
= -100 A
V
O
= V
DD
and V
SS
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
= 1MHz @ 0V
= 1MHz @ 0V
15
15
pF
pF
2.0
10
1.6
mW/MHz
A
mA
-12
mA
.7V
DD
V
DD
- 0.25
-30
30
.5V
DD
.7V
DD
-1
1
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
A
0.40
0.25
V
V
OH
V
I
OZ
I
OS
I
OL
A
-300
12
300
mA
mA
RadHard MSI Logic
168
UT54ACS245/UT54ACTS245
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
Hardware platform: C6678 evaluation board I want to set up a global data structure, each core has read permission, and each core has write permission for the part it is responsible for. May I ask: How...
[color=black][b][size=2]【PDF】[/size][/b][size=3]Automobile air conditioning inverter power supply control system and its implementation[/size][/color]...
CPU: C28 Instructions used: RPT #15 || PREAD *XAR0++, *XAR7 Purpose: Transfer the values of 16 registers at a time. XAR0 already points to the destination address, and XAR7 already points to the sourc...
Yesterday afternoon, I was planting rice in the rice field when I received a call from the courier. They asked where it was sent from and said it was from Texas Instruments. I was surprised at the tim...
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
