M392B5673FH0-YK0 datasheet, PDF

Datasheet> All Categories > storage> storage> M392B5673FH0-YK0

M392B5673FH0-YK0: DescriptionDDR DRAM Module, 256MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size922KB，46 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

Download Datasheet Parametric Compare View All

M392B5673FH0-YK0 Overview

DDR DRAM Module, 256MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240

M392B5673FH0-YK0 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	240
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	0.225 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N240
memory density	19327352832 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	240
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature
organize	256MX72
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	1.45 V
Minimum supply voltage (Vsup)	1.2825 V
Nominal supply voltage (Vsup)	1.35 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal location	DUAL

Preview

Download Datasheet

View All

VLP Registered DIMM

DDR3L SDRAM

DDR3L SDRAM Specification

240pin VLP Registered DIMM based on 1Gb F-die

72-bit ECC

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 46

Rev. 0.9 September 2009

VLP Registered DIMM

Table Contents

DDR3L SDRAM

1.0 DDR3L Registered DIMM Ordering Information ........................................................................5

2.0 Key Features .................................................................................................................................5

3.0 Address Configuration .................................................................................................................5

4.0 Registered DIMM Pin Configurations (Front side/Back side) ...................................................6

5.0 Pin Description .............................................................................................................................7

6.0 ON DIMM Thermal Sensor ............................................................................................................7

7.0 Input/Output Functional Description ..........................................................................................8

8.0 Pinout comparison Based on Module Type ...............................................................................9

9.0 Registering Clock Driver Specification ....................................................................................10

9.1 Timing & Capacitance values

.......................................................................................................10

9.2 Clock driver Characteristics

........................................................................................................10

10.0 Functional Block Diagram: ......................................................................................................11

10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

.................................................11

10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

................................................12

10.3 2GB, 256Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs)

.................................................13

10.4 4GB, 512Mx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)

................................................14

10.5 4GB, 512Mx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs)

................................................15

11.0 Absolute Maximum Ratings .....................................................................................................16

11.1 Absolute Maximum DC Ratings

..................................................................................................16

11.2 DRAM Component Operating Temperature Range

........................................................................16

12.0 AC & DC Operating Conditions ...............................................................................................16

12.1 Recommended DC Operating Conditions (SSTL)

..........................................................................16

13.0 AC & DC Input Measurement Levels .......................................................................................17

13.1 AC & DC Logic Input Levels for Single-ended Signals

...................................................................17

13.2 V

REF

Tolerances

.......................................................................................................................18

13.3 AC and DC Logic Input Levels for Differential Signals

...................................................................19

13.3.1 Differential Signals Definition

..............................................................................................19

13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

............................19

13.3.3 Single-ended Requirements for Differential Signals

...............................................................20

13.3.4 Differential Input Cross Point Voltage

...................................................................................21

13.4 Slew Rate Definition for Single Ended Input Signals

.....................................................................21

13.5 Slew Rate Definition for Differential Input Signals

.........................................................................21

14.0 AC and DC Output Measurement Levels ................................................................................22

14.1 Single Ended AC and DC Output Levels

......................................................................................22

14.2 Differential AC and DC Output Levels

..........................................................................................22

14.3 Single Ended Output Slew Rate

..................................................................................................22

2 of 46

Rev. 0.9 September 2009

VLP Registered DIMM

14.4 Differential Output Slew Rate

DDR3L SDRAM

.....................................................................................................23

15.0 IDD specification definition .....................................................................................................24

15.1 IDD SPEC Table

........................................................................................................................26

16.0 Input/Output Capacitance ........................................................................................................29

17.0 Electrical Characteristics and AC timing ...............................................................................30

17.1 Refresh Parameters by Device Density

........................................................................................30

17.2 Speed Bins and CL, tRCD, tRC and tRAS for Corresponding Bin

....................................................30

17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

..............................................31

17.3.1 Speed Bin Table Notes

.......................................................................................................34

18.0 Timing Parameters for DDR3-800, DDR3-1066, DDR3-1333 and DDR3-1600 ......................35

18.1 Jitter Notes

..............................................................................................................................38

18.2 Timing Parameter Notes

............................................................................................................39

19.0 Physical Dimensions : ..............................................................................................................40

19.1 128Mbx8 based 128Mx72 Module(1 Rank)

....................................................................................40

.............................................40

19.2 128Mbx8 based 256Mx72 Module(2 Ranks)

.................................................................................41

19.2.1 x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs

............................................41

19.3 256Mbx4 based 256Mx72 Module(1 Rank)

....................................................................................42

19.3.1 x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs

.............................................42

19.4 256Mbx4(DDP) based 512Mx72 Module(2 Ranks)

..........................................................................43

19.4.1 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs

..................................................43

19.5 512Mbx8(DDP) based 512Mx72 Module(4 Ranks)

..........................................................................44

19.5.1 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs

.................................................44

19.5.2 Heat Spreader Design Guide

...............................................................................................45

19.1.1 x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs

3 of 46

Rev. 0.9 September 2009

M392B5673FH0-YK0 Related Products

	M392B5673FH0-YK0	M392B2873FH0-YK0	M392B5170FM0-YK0	M392B5173FM0-YK0	M392B5173FM0-YH9	M392B5173FM0-YF8	M392B5670FH0-YK0
Description	DDR DRAM Module, 256MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 128MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.3ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 256MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
Parts packaging code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,
Contacts	240	240	240	240	240	240	240
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	SINGLE BANK PAGE BURST	DUAL BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	SINGLE BANK PAGE BURST
Maximum access time	0.225 ns	0.225 ns	0.225 ns	0.225 ns	0.255 ns	0.3 ns	0.225 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240
memory density	19327352832 bit	9663676416 bit	38654705664 bit	38654705664 bit	38654705664 bit	38654705664 bit	19327352832 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	72	72	72	72	72	72	72
Number of functions	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1
Number of terminals	240	240	240	240	240	240	240
word count	268435456 words	134217728 words	536870912 words	536870912 words	536870912 words	536870912 words	268435456 words
character code	256000000	128000000	512000000	512000000	512000000	512000000	256000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C
organize	256MX72	128MX72	512MX72	512MX72	512MX72	512MX72	256MX72
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
self refresh	YES	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V
Minimum supply voltage (Vsup)	1.2825 V	1.2825 V	1.2825 V	1.2825 V	1.2825 V	1.2825 V	1.2825 V
Nominal supply voltage (Vsup)	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V
surface mount	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maker	SAMSUNG	-	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG

Recommended Resources

Circuit 2 for synchronously controlling motors with two frequency converters

Thyristor overcurrent protection circuit 2

SAF1039P (TV, audio equipment and industrial control equipment) infrared remote control receiving and decoding circuit

Portable thyristor charger circuit

Inverting adding circuit

Bistable counting base trigger circuit

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components