1. No connect (NC) pins are left unconnected or floating. Connecting any of these pins to the positive or negative power supply causes improper operation or failure of
the device.
2. Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ.
Use VCCQ for compatibility with next generation of OC-48 SERDES devices.
Document Number: 38-02009 Rev. *L
FIFO_ERR
RXD[10]
RXD[11]
RXD[9]
VSSN
VREF
Page 4 of 18
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CYS25G0101DX
Pin Descriptions
Table 1. CYS25G0101DX OC-48 SONET Transceiver
Pin Name
TXD[15:0]
TXCLKI
I/O Characteristics
Signal Description
Transmit Path Signals
HSTL inputs,
Parallel Transmit Data Inputs.
A 16-bit word, sampled by TXCLKI↑. TXD[15] is the most
sampled by TXCLKI↑ significant bit (the first bit transmitted).
HSTL Clock input
Parallel Transmit Data Input Clock.
The TXCLKI is used to transfer the data into the input
register of the serializer. The TXCLKI samples the data, TXD [15:0], on the rising edge of
the clock cycle.
Transmit Clock Output.
Divide by 16 of the selected transmit bit rate clock. It is used to
coordinate byte wide transfers between upstream logic and the CYS25G0101DX.
Reference Voltage for HSTL Parallel Input Bus.
V
DDQ
/2.
[3]
TXCLKO
V
REF
HSTL Clock output
Input Analog
Reference
HSTL output,
synchronous
HSTL Clock output
Analog
Analog
Analog
Analog
Analog
Differential LVPECL
input
LVTTL output
Receive Path Signals
RXD[15:0]
RXCLK
CM_SER
RXCN1
RXCN2
RXCP1
RXCP2
REFCLK±
Parallel Receive Data Output.
These outputs change following RXCLK↓. RXD[15] is the
most significant bit of the output word and is received first on the serial interface.
Receive Clock Output.
Divide by 16 of the bit rate clock extracted from the received serial
stream. RXD [15:0] is clocked out on the falling edge of the RXCLK.
Common Mode Termination.
Capacitor shunt to V
SS
for common mode noise.
Receive Loop Filter Capacitor (Negative).
Receive Loop Filter Capacitor (Negative).
Receive Loop Filter Capacitor (Positive).
Receive Loop Filter Capacitor (Positive).
Reference Clock.
This clock input is used as the timing reference for the transmit and
receive PLLs. A derivative of this input clock is used to clock the transmit parallel interface.
The reference clock is internally biased enabling for an AC coupled clock signal.
Line Fault Indicator.
When LOW, this signal indicates that the selected receive data
stream is detected as invalid by either a LOW input on SD or by the receive VCO operated
outside its specified limits.
Reset for all logic functions except the transmit FIFO.
Receive PLL Lock to Reference.
When LOW, the receive PLL locks to REFCLK instead
of the received serial data stream.
Signal Detect.
When LOW, the receive PLL locks to REFCLK instead of the received serial
data stream. The SD needs to be connected to an external optical module to indicate a
loss of received optical power.
Transmit FIFO Error.
When HIGH, the transmit FIFO has either underflowed or
overflowed. When this occurs, the FIFO’s internal clearing mechanism clears the FIFO
within nine clock cycles. In addition, FIFO_RST is activated at device power up to ensure
that the in and out pointers of the FIFO are set to maximum separation.
Transmit FIFO Reset.
When LOW, the in and out pointers of the transmit FIFO are set to
maximum separation. FIFO_RST is activated at device power up to ensure that the in and
out pointers of the FIFO are set to maximum separation. When the FIFO is reset, the output
data is a 1010... pattern.
Device Power Down.
When LOW, the logic and drivers are all disabled and placed into a
standby condition where only minimal power is dissipated.
Device Control and Status Signals
LFI
RESET
LOCKREF
SD
LVTTL input
LVTTL input
LVTTL input
FIFO_ERR
LVTTL output
FIFO_RST
LVTTL input
PWRDN
LVTTL input
Note
3. V
REF
equals to (V
CC
– 1.33V) if interfacing to a parallel LVPECL interface.
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