The MM54C174 MM74C174 hex D flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed
with N- and P-channel enhancement transistors All have a
direct clear input Information at the D inputs meeting the
setup time requirements is transferred to the Q outputs on
the positive-going edge of the clock pulse Clear is indepen-
dent of clock and accomplished by a low level at the clear
input All inputs are protected by diodes to V
CC
and GND
Features
Y
Y
Y
Y
Wide supply voltage range
Guaranteed noise margin
High noise immunity
Low power TTL compatibility
3 0V to 15V
1 0V
0 45 V
CC
(typ )
Fan out of 2
driving 74L
Logic and Connection Diagrams
TL F 5899 – 2
TL F 5899 – 1
TL F 5899 – 3
Dual-In-Line Package
Truth Table
Inputs
Clear
L
H
H
H
Clock
X
D
X
H
L
X
Output
Q
L
H
L
Q
u
u
L
TL F 5899 – 4
Top View
Order Number MM54C174 or MM74C174
C
1995 National Semiconductor Corporation
TL F 5899
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
b
0 3V to V
CC
a
0 3V
Voltage at Any Pin
Operating Temperature Range
MM54C174
MM74C174
b
55 C to
a
125 C
b
40 C to
a
85 C
Storage Temperature Range
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Operating V
CC
Range
Absolute Maximum V
CC
Lead Temperature (Soldering 10 sec )
b
65 C to
a
150 C
700 mW
500 mW
3 0V to 15V
18V
260 C
DC Electrical Characteristics
Min
Symbol
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Supply Current
Parameter
Max limits apply across temperature range unless otherwise specified
Conditions
Min
Typ
Max
Units
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V I
O
e b
10
mA
V
CC
e
10V I
O
e b
10
mA
V
CC
e
5V I
O
e
10
mA
V
CC
e
10V I
O
e
10
mA
V
CC
e
15V V
IN
e
15V
V
CC
e
15V V
IN
e
0V
V
CC
e
15V
35
80
15
20
45
90
05
10
0 005
b
1 0
b
0 005
V
V
V
V
V
V
V
V
mA
mA
300
mA
10
0 05
CMOS LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
54C V
CC
e
4 5V
74C V
CC
e
4 75V
54C V
CC
e
4 5V
74C V
CC
e
4 75V
54C V
CC
e
4 5V I
O
e b
360
mA
74C V
CC
e
4 75V I
O
e b
360
mA
54C V
CC
e
4 5V I
O
e
360
mA
74C V
CC
e
4 75V I
O
e
360
mA
24
24
04
04
V
CC
b
1 5
V
CC
b
1 5
08
08
V
V
V
V
V
V
V
V
OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (short circuit current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Output Source Current
(P-Channel)
Output Source Current
(P-Channel)
Output Sink Current
(N-Channel)
Output Sink Current
(N-Channel)
V
CC
e
5V
T
A
e
25 C V
OUT
e
0V
V
CC
e
10V
T
A
e
25 C V
OUT
e
0V
V
CC
e
5V
T
A
e
25 C V
OUT
e
0V
V
CC
e
5V
T
A
e
25 C V
OUT
e
0V
b
1 75
b
8 0
b
3 3
b
15
mA
mA
mA
mA
1 75
80
36
16
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
2
AC Electrical Characteristics
Symbol
t
pd
t
pd
t
S1
t
S0
t
H1
t
H0
t
W
t
W
t
r
t
f
f
MAX
C
IN
C
PD
Parameter
T
A
e
25 C C
L
e
50 pF unless otherwise noted
Conditions
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
Clear Input (Note 2)
Any Other Input
Per Package (Note 3)
15
50
20
50
75
25
0
0
b
10
b
5 0
Min
Typ
150
70
110
50
Max
300
110
300
110
Units
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay Time to a Logical
‘‘0’’ or Logical ‘‘1’’ from Clock to Q
Propagation Delay Time to
a Logical ‘‘0’’ from Clear
Time Prior to Clock Pulse that
Data Must be Present
Time after Clock Pulse
that Data Must be Held
Minimum Clock Pulse Width
Minimum Clear Pulse Width
Maximum Clock Rise and
Fall Time
Maximum Clock Frequency
Input Capacitance
Power Dissipation Capacitance
50
35
65
35
l
1200
l
1200
250
100
140
70
ns
ns
ns
ns
ms
ms
MHz
MHz
pF
pF
pF
65
12
11
50
95
AC Parameters are guaranteed by DC correlated testing
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2
Capacitance is guaranteed by periodic testing
Note 3
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note
AN-90
Switching Time Waveforms
CMOS to CMOS
AC Test Circuit
TL F 5899 – 6
TL F 5899 – 5
t
r
e
t
f
e
20 ns
3
MM54C174 MM74C174 Hex D Flip-Flop
Physical Dimensions
inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C174J or MM74C174J
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number MM54C174N or MM74C174N
NS Package Number N16E
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