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DS1012M-V20

Description
Silicon Delay Line, 2-Func, 1-Tap, True Output, CMOS, PDIP8, 0.300 INCH, DIP-8
Categorylogic    logic   
File Size52KB,7 Pages
ManufacturerDALLAS
Websitehttp://www.dalsemi.com
Download Datasheet Parametric View All

DS1012M-V20 Overview

Silicon Delay Line, 2-Func, 1-Tap, True Output, CMOS, PDIP8, 0.300 INCH, DIP-8

DS1012M-V20 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instruction0.300 INCH, DIP-8
Reach Compliance Codeunknow
Other featuresOUT3 = D3 NAND D4, OUT4 = D3 NOR D4
series1000
Input frequency maximum value (fmax)3.33333 MHz
JESD-30 codeR-PDIP-T8
JESD-609 codee0
Logic integrated circuit typeSILICON DELAY LINE
Number of functions2
Number of taps/steps1
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP8,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)70 mA
programmable delay lineNO
Prop。Delay @ Nom-Su50 ns
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Total delay nominal (td)50 ns
Base Number Matches1
DS1012
DS1012
2-in-1 Sub-Miniature Silicon
Delay Line with Logic
FEATURES
PIN ASSIGNMENT
IN1
OUT3
OUT1
GND
1
2
3
4
8
7
6
5
V
CC
IN2
OUT2
OUT4
All-silicon time delay
53
µW
max. CMOS quiescent mode
Surface mount 8-pin mini-SOIC and standard 8-pin
DIP
2 independent buffered delays per input
Option of complemented output(s)
Option of timed AND, NAND, OR, NOR, XOR, XNOR,
HALF-XOR and HALF-XNOR logic outputs
DS1012M 8-PIN DIP (300 MIL)
See Mech. Drawings
Section
IN1
OUT3
OUT1
GND
1
2
3
4
8
7
6
5
V
CC
IN2
OUT2
OUT4
Delay tolerance:
±1.5
ns (delays: 3-10 ns),
±2.0
ns (delays: 11-40 ns)
Vapor phase, IR and wave solderability
Economical
TTL/CMOS-compatible
Quick turn prototypes
Custom delays and logic options available
DS1012Z 8-PIN SOIC (150 MIL)
See Mech. Drawings
Section
PIN DESCRIPTION
IN1, IN2
OUT1, OUT2
OUT3, OUT4
GND
V
CC
Inputs
Outputs (delays)
Outputs (delays, logic)
Ground
+5 Volts
DESCRIPTION
In its most simple configuration, the DS1012 2-in-1
Sub-Miniature Silicon Delay Line Chip provides two in-
puts, each of which in turn provides independent delays
to a pair of outputs. The DS1012-1 and DS1012-3 are
examples of catalog parts having this basic configura-
tion. Any of the four outputs can be inverted at the time
of manufacture.
For applications requiring two-input timed logic func-
tions, at the time of manufacture the simple delay on
OUT4 can be replaced by one of the following: OR,
NOR, XOR, or XNOR. Similarly, a timed AND, NAND,
HALF-XOR (D3 AND D4), or NOT HALF-XOR (D3 OR
D4) can be substituted for the simple delay on OUT3.
DS1012-2, DS1012-4, and DS1012-5 are examples of
catalog parts configured with logic functions on OUT3
and OUT4. Note that DS1012-2 also utilizes an output
inversion on OUT2.
In any configuration, delays D1 (t
D1
) and D2 (t
D2
) can be
specified within the range of ~3 ns to 10 ns. Delays D3
(t
D3
) and D4 (t
D4
) can be specified to have values be-
tween ~3 ns and 40 ns. The worst case leading edge
delay accuracy at nominal voltage and room tempera-
ture is
±2
ns. The DS1012 is offered in two packages: an
8-pin DIP and an 8-pin 150 mil wide mini-SOIC.
Dallas Semiconductor offers the DS1012 in a wide vari-
ety of custom delay and logic configurations. For special
requests and quick turn delivery, call (972) 371–4348.
021798 1/7

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