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AM29F040-90ECB

Description
512K X 8 FLASH 5V PROM, 90 ns, PQCC32
Categorystorage    storage   
File Size145KB,33 Pages
ManufacturerAMD
Websitehttp://www.amd.com
Download Datasheet Parametric View All

AM29F040-90ECB Overview

512K X 8 FLASH 5V PROM, 90 ns, PQCC32

AM29F040-90ECB Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAMD
Parts packaging codeTSOP
package instructionTSOP1, TSSOP32,.8,20
Contacts32
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum access time90 ns
command user interfaceYES
Data pollingYES
Durability100000 Write/Erase Cycles
JESD-30 codeR-PDSO-G32
JESD-609 codee0
length18.4 mm
memory density4194304 bi
Memory IC TypeFLASH
memory width8
Number of functions1
Number of departments/size8
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP1
Encapsulate equivalent codeTSSOP32,.8,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Department size64K
Maximum standby current0.000005 A
Maximum slew rate0.04 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
switch bitYES
typeNOR TYPE
width8 mm
FINAL
Am29F040
4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s
5.0 V
±
10% for read and write operations
— Minimizes system level power requirements
s
Compatible with JEDEC-standards
— Pinout and software compatible with single-
power-supply Flash
— Superior inadvertent write protection
s
Package options
— 32-pin PLCC
— 32-pin TSOP
s
s
s
— 32-pin PDIP
Minimum 100,000 write/erase cycles guaranteed
High performance
— 55 ns maximum access time
Sector erase architecture
— Uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
Also supports full chip erase.
Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations
s
Embedded Erase Algorithms
— Automatically preprograms and erases the chip
or any combination of sectors
s
Embedded Program Algorithms
— Automatically programs and verifies data at
specified address
s
Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
s
Erase suspend/resume
— Supports reading data from a sector not being
erased
s
Low power consumption
— 20 mA typical active read current
— 30 mA typical program/erase current
s
Enhanced power management for standby
mode
— <1
µ
A typical standby current
— Standard access time from standby mode
s
GENERAL DESCRIPTION
The Am29F040 is a 4 Mbit, 5.0 Volt-only Flash memory
organized as 512 Kbytes of 8 bits each. The Am29F040
is offered in a 32-pin package. This device is designed
to be programmed in-system with the standard system
5.0 V V
CC
supply. A 12.0 V V
PP
is not required for
write or erase operations. The device can also be
reprogrammed in standard EPROM programmers.
The standard Am29F040 offers access times between
55 ns and 150 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus
contention the device has separate chip enable (CE),
write enable (WE) and output enable (OE) controls.
The Am29F040 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine
which controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 Volt Flash or EPROM devices.
The Am29F040 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Typically, each sector can
be programmed and verified in less than one second.
Erase is accomplished by executing the erase com-
mand sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automati-
cally preprograms the array if it is not already pro-
grammed before executing the erase operation. During
erase, the device automatically times the erase pulse
widths and verifies proper cell margin.
Publication#
17113
Rev:
E
Amendment/0
Issue Date:
November 1996
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