XC17256ELPCG20I datasheet, PDF

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XC17256ELPCG20I: DescriptionConfiguration Memory, 256KX1, Serial, CMOS, PQCC20, PLASTIC, LCC-20; Categorystorage storage; File Size249KB，13 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/; Environmental Compliance

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XC17256ELPCG20I Overview

Configuration Memory, 256KX1, Serial, CMOS, PQCC20, PLASTIC, LCC-20

XC17256ELPCG20I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	XILINX
Parts packaging code	QLCC
package instruction	QCCJ,
Contacts	20
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	USED FOR STORING THE CONFIGURATION BITSTREAMS OF XILINX FPGAS
JESD-30 code	S-PQCC-J20
JESD-609 code	e3
length	8.9662 mm
memory density	262144 bit
Memory IC Type	CONFIGURATION MEMORY
memory width	1
Humidity sensitivity level	3
Number of functions	1
Number of terminals	20
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX1
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	8.9662 mm

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Product Obsolete or Under Obsolescence

XC1700E, XC1700EL, and XC1700L

Series Configuration PROMs

Product Specification

DS027 (v3.5) June 25, 2008

Features

•

One-time programmable (OTP) read-only memory

designed to store configuration bitstreams of Xilinx

FPGAs

Simple interface to the FPGA; requires only one user

I/O pin

Cascadable for storing longer or multiple bitstreams

Programmable reset polarity (active High or active

Low) for compatibility with different FPGA solutions

XC17128E/EL, XC17256E/EL, XC1701, and XC1700L

series support fast configuration

Low-power CMOS floating-gate process

•

XC1700E series are available in 5V and 3.3V versions

XC1700L series are available in 3.3V only

Available in compact plastic packages: 8-pin SOIC, 8-

pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-

pin PLCC or 44-pin VQFP

Programming support by leading programmer

manufacturers

Design support using the Xilinx Alliance and

Foundation™ software packages

Guaranteed 20 year life data retention

Lead-free (Pb-free) packaging available

•

Description

The XC1700 family of configuration PROMs provides an

easy-to-use, cost-effective method for storing large Xilinx

FPGA configuration bitstreams. See

Figure 1

for a

simplified block diagram.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising clock edge, data appears on the PROM

DATA output pin that is connected to the FPGA D

pin. The

FPGA generates the appropriate number of clock pulses to

complete the configuration. After configured, it disables the

PROM. When the FPGA is in Slave Serial mode, the PROM

and the FPGA must both be clocked by an incoming signal.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family.

For device programming, either the Xilinx Alliance or

Foundation software compiles the FPGA design file into a

standard Hex format, which is then transferred to most

commercial PROM programmers.

X-Ref Target - Figure 1

VCC

VPP

GND

RESET/

OE/

RESET

CEO

CLK

Address Counter

EPROM

Cell

Matrix

Output

DATA

DS027_01_021500

Figure 1:

Simplified Block Diagram (Does Not Show Programming Circuit)

other countries. All other trademarks are the property of their respective owners.

DS027 (v3.5) June 25, 2008

Product Specification

www.xilinx.com

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