SN54ALS112AFK datasheet, PDF - EEWORLD Datasheet

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SN54ALS112AFK: DescriptionJ-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20, CERAMIC, CC-20; Categorylogic logic; File Size183KB，9 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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SN54ALS112AFK Overview

J-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20, CERAMIC, CC-20

SN54ALS112AFK Parametric

Parameter Name	Attribute value
Maker	Rochester Electronics
package instruction	QCCN,
Reach Compliance Code	unknown
series	ALS
JESD-30 code	S-CQCC-N20
length	8.89 mm
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Package shape	SQUARE
Package form	CHIP CARRIER
propagation delay (tpd)	24 ns
Maximum seat height	2.03 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	TTL
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
Trigger type	NEGATIVE EDGE
width	8.89 mm
minfmax	25 MHz

SN54ALS112AFK Preview

SN54ALS112A, SN74ALS112A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS199A – APRIL 1982 – REVISED DECEMBER 1994

•

Fully Buffered to Offer Maximum Isolation

From External Disturbance

Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

TYPICAL MAXIMUM

CLOCK

FREQUENCY

(MHz)

TYPICAL POWER

DISSIPATION

PER FLIP-FLOP

(mW)

SN54ALS112A . . . J PACKAGE

SN74ALS112A . . . D OR N PACKAGE

(TOP VIEW)

TYPE

′ALS112A

1CLK

1PRE

GND

1CLR

2CLR

2CLK

2PRE

description

These devices contain two independent J-K

negative-edge-triggered flip-flops. A low level at

the preset (PRE) or clear (CLR) inputs sets or

resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive

(high), data at the J and K inputs meeting the

setup-time requirements is transferred to the

outputs on the negative-going edge of the clock

pulse (CLK). Clock triggering occurs at a voltage

level and is not directly related to the fall time of the

clock pulse. Following the hold-time interval, data

at the J and K inputs may be changed without

affecting the levels at the outputs. These versatile

flip-flops can perform as toggle flip-flops by tying

J and K high.

SN54ALS112A . . . FK PACKAGE

(TOP VIEW)

1PRE

2 1 20 19

1CLR

2CLR

2CLK

NC – No internal connection

The SN54ALS112A is characterized for operation over the full military temperature range of – 55°C to 125°C.

The SN74ALS112A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

PRE

CLR

CLK

↓

OUTPUTS

H†

Toggle

H†

† The output levels in this configuration may not meet the

minimum levels for VOH. Furthermore, this configuration is

nonstable; that is, it does not persist when either PRE or

CLR returns to its inactive (high) level.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1994, Texas Instruments Incorporated

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

GND

2PRE

1CLK

9 10 11 12 13

SN54ALS112A, SN74ALS112A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS199A – APRIL 1982 – REVISED DECEMBER 1994

logic symbol

†

1PRE

1CLK

1CLR

2PRE

2CLK

2CLR

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

logic diagram (positive logic)

PRE

CLK

CLR

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Input voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Operating free-air temperature range, T

: SN54ALS112A . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C

SN74ALS112A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

SN54ALS112A, SN74ALS112A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS199A – APRIL 1982 – REVISED DECEMBER 1994

recommended operating conditions

SN54ALS112A

MIN

VCC

VIH

VIL

IOH

IOL

fclock

Supply voltage

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Clock frequency

PRE or CLR low

Pulse duration

CLK high

CLK low

tsu

Data

Setup

Set p time before CLK↓

Hold time after CLK↓

Operating free-air temperature

PRE or CLR inactive

Data

– 55

125

4.5

0.7

– 0.4

16.5

°C

NOM

MAX

5.5

SN74ALS112A

MIN

4.5

0.8

– 0.4

NOM

MAX

5.5

UNIT

MHz

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

VIK

VOH

VOL

IIH

IIL

J, K, or CLK

PRE or CLR

J, K, or CLK

PRE or CLR

J, K, or CLK

PRE or CLR

TEST CONDITIONS

VCC = 4.5 V,

VCC = 4.5 V to 5.5 V,

VCC = 4 5 V

4.5

VCC = 5 5 V

5.5 V,

VCC = 5 5 V

5.5 V,

VCC = 5 5 V

5.5 V,

II = –18 mA

IOH = – 0.4 mA

IOL = 4 mA

IOL = 8 mA

VI = 7 V

VI = 2 7 V

2.7

VI = 0 4 V

0.4

SN54ALS112A

MIN TYP†

MAX

–1.5

VCC – 2

0.25

0.4

0.1

0.2

– 0.2

– 0.4

VCC – 2

0.25

0.35

0.4

0.5

0.1

0.2

– 0.2

– 0.4

SN74ALS112A

MIN TYP†

MAX

–1.5

UNIT

µA

IO‡

VCC = 5.5 V,

VO = 2.25 V

– 20

–112

– 30

–112

ICC

VCC = 5.5 V,

See Note 1

2.5

4.5

2.5

4.5

† All typical values are at VCC = 5 V, TA = 25°C.

‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

SN54ALS112A, SN74ALS112A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS199A – APRIL 1982 – REVISED DECEMBER 1994

switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

RL = 500

Ω,

TA = MIN to MAX†

SN54ALS112A SN74ALS112A

MIN

fmax

tPLH

tPHL

tPLH

PRE or CLR

CLK

Q or Q

MAX

MIN

MAX

MHz

PARAMETER

FROM

(INPUT)

(OUTPUT)

UNIT

tPHL

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

SN54ALS112A, SN74ALS112A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS199A – APRIL 1982 – REVISED DECEMBER 1994

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

VCC

From Output

Under Test

(see Note A)

Test

Point

From Output

Under Test

(see Note A)

Test

Point

From Output

Under Test

(see Note A)

Test

Point

RL = R1 = R2

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

Timing

Input

tsu

Data

Input

1.3 V

3.5 V

1.3 V

0.3 V

3.5 V

1.3 V

0.3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

High-Level

Pulse

3.5 V

1.3 V

0.3 V

Low-Level

Pulse

3.5 V

1.3 V

0.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

Output

Control

(low-level

enabling)

tPZL

Waveform 1

S1 Closed

(see Note B)

3.5 V

1.3 V

0.3 V

tPLZ

1.3 V

VOL

0.3 V

VOH

1.3 V

0.3 V

3.5 V

Input

tPLH

In-Phase

Output

1.3 V

0.3 V

tPHL

VOH

1.3 V

VOL

tPLH

VOH

1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

1.3 V

VOL

[

3.5 V

tPHZ

tPZH

Waveform 2

S1 Open

(see Note B)

tPHL

Out-of-Phase

Output

(see Note C)

[

0 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. When measuring propagation delay items of 3-state outputs, switch S1 is open.

D. All input pulses have the following characteristics: PRR

≤

1 MHz, tr = tf = 2 ns, duty cycle = 50%.

E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

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