TS80C52X2-VJBB datasheet, PDF - EEWORLD Datasheet

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TS80C52X2-VJBB: DescriptionMicrocontroller, 8-Bit, MROM, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size791KB，56 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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TS80C52X2-VJBB Overview

Microcontroller, 8-Bit, MROM, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44

TS80C52X2-VJBB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	44
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Has ADC	NO
Address bus width	16
bit size	8
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQCC-J44
JESD-609 code	e3
length	16.5862 mm
Humidity sensitivity level	2
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	245
Certification status	Not Qualified
ROM programmability	MROM
Maximum seat height	4.57 mm
speed	40 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	16.5862 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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TS80C32X2

TS87C52X2

TS80C52X2

8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless

1. Description

TS80C52X2 is high performance CMOS ROM, OTP,

EPROM and ROMless versions of the 80C51 CMOS

single chip 8-bit microcontroller.

The TS80C52X2 retains all features of the 80C51 with

extended ROM/EPROM capacity (8 Kbytes), 256 bytes

of internal RAM, a 6-source , 4-level interrupt system,

an on-chip oscilator and three timer/counters.

In addition, the TS80C52X2 has a dual data pointer, a

more versatile serial channel that facilitates

multiprocessor communication (EUART) and a X2 speed

improvement mechanism.

The fully static design of the TS80C52X2 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The TS80C52X2 has 2 software-selectable modes of

reduced activity for further reduction in power

consumption. In the idle mode the CPU is frozen while

the timers, the serial port and the interrupt system are still

operating. In the power-down mode the RAM is saved

and all other functions are inoperative.

2. Features

80C52 Compatible

•

8051 pin and instruction compatible

•

Four 8-bit I/O ports

•

Three 16-bit timer/counters

•

256 bytes scratchpad RAM

Interrupt Structure with

•

6 Interrupt sources,

•

4 level priority interrupt system

Full duplex Enhanced UART

•

Framing error detection

•

Automatic address recognition

High-Speed Architecture

•

40 MHz @ 5V, 30MHz @ 3V

•

X2 Speed Improvement capability (6 clocks/

machine cycle)

30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

60 MHz @ 5V, 40 MHz @ 3V)

Low EMI (inhibit ALE)

Power Control modes

•

Idle mode

•

Power-down mode

•

Power-off Flag

Dual Data Pointer

On-chip ROM/EPROM (8Kbytes)

Programmable Clock Out and Up/Down Timer/

Counter 2

Asynchronous port reset

Once mode (On-chip Emulation)

Power supply: 4.5-5.5V, 2.7-5.5V

Temperature ranges: Commercial (0 to 70

C) and

Industrial (-40 to 85

Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1

(13.9 footprint), CQPJ44 (window), CDIL40

(window)

Rev.D - 16 November, 2000

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