INTEGRATED CIRCUITS
DATA SHEET
74ALVCH162601
18-bit universal bus transceiver with
30
Ω
termination resistor; 3-state
Product specification
File under Integrated Circuits, IC24
1999 Oct 14
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30
Ω
termination resistor; 3-state
FEATURES
•
Complies with JEDEC standard
no. 8-1A
•
CMOS low power consumption
•
Direct interface with TTL levels
•
MULTIBYTE™ flow-through
standard pin-out architecture
•
Low inductance multiple V
CC
and
ground pins for minimum noise and
ground bounce
•
All data inputs have bus hold
circuitry
•
Integrated 30
Ω
termination
resistors.
DESCRIPTION
74ALVCH162601
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting
3-state bus compatible outputs in both send and receive directions. Data flow
in each direction is controlled by output enable (OE
AB
and OE
BA
), and clock
(CP
AB
and CP
BA
) inputs. For A-to-B data flow, the device operates in the
transparent mode when LE
AB
is HIGH. When LE
AB
is LOW, the A data is
latched if CP
AB
is held at a HIGH or LOW logic level. If LE
AB
is LOW, the A-bus
data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CP
AB
.
When OE
AB
is LOW, the outputs are active. When OE
AB
is HIGH, the outputs
are in the high-impedance state. The clocks can be controlled with the
clock-enable inputs (CE
BA
/CE
AB
).
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
.
To ensure the high-impedance state during power-down, OE
BA
and OE
AB
should be tied to V
CC
through a pull-up resistor, the minimum value of the
resistor is determined by the current-sinking/current-sourcing capability of the
driver.
The 74ALVCH162601 is designed with 30
Ω
series resistors in both HIGH or
LOW output stage.
Active bus hold circuitry is provided to hold unused or floating data inputs at
a valid logic level.
QUICK REFERENCE DATA
Ground = 0; T
amb
= 25
°C;
t
r
= t
f
= 2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I/O
C
I
C
PD
PARAMETER
propagation delay A
n
, B
n
to B
n
, A
n
input/output capacitance
input capacitance
power dissipation capacitance per
latch
notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
21
3
pF
pF
CONDITIONS
C
L
= 30 pF; V
CC
= 2.5 V
C
L
= 50 pF; V
CC
= 3.3 V
TYPICAL
4.0
3.1
8.0
4.0
ns
ns
pF
pF
UNIT
1999 Oct 14
2
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30
Ω
termination resistor; 3-state
FUNCTION TABLE
See note 1.
INPUTS
74ALVCH162601
OUTPUTS
CE
XX
X
X
X
H
L
L
L
L
Note
1. XX = AB for A-to-B direction, BA for B-to-A direction;
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of CP
XX
;
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of CP
XX
;
X = don’t care;
↑
= LOW-to-HIGH level transition;
NC = no change;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
74ALVCH162601DGG
−40
to +85
°C
PINS
56
PACKAGE
TSSOP
MATERIAL
plastic
OE
XX
H
L
L
L
L
L
L
L
LE
XX
X
H
H
L
L
L
L
L
CP
XX
X
X
X
X
↑
↑
L
H
A
n
, B
n
X
H
L
X
h
l
X
X
Z
H
L
NC
H
L
NC
STATUS
disabled
transparent
hold
clock and display
hold
CODE
SOT364-1
1999 Oct 14
3
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30
Ω
termination resistor; 3-state
PINNING
PIN
1
2
OE
AB
LE
AB
SYMBOL
74ALVCH162601
DESCRIPTION
output enable A-to-B
latch enable A-to-B
data inputs/outputs
ground (0 V)
DC supply voltage
output enable B-to-A
latch enable B-to-A
clock enable B-to-A
clock input B-to-A
data inputs/outputs
3, 5, 6, 8, 9, 10, 12, 13, 14, 15, A
0
to A
17
16, 17, 19, 20, 21, 23, 24, 26
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
27
28
29
30
31, 33, 34, 36, 37, 38, 40, 41,
42, 43, 44, 45, 47, 48, 49, 51,
52, 54
55
56
GND
V
CC
OE
BA
LE
BA
CE
BA
CP
BA
B
17
to B
0
CP
AB
CE
AB
clock input A-to-B
clock enable A-to-B
1999 Oct 14
4
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30
Ω
termination resistor; 3-state
74ALVCH162601
handbook, halfpage
OEAB
LEAB
A0
GND
A1
A2
VCC
A3
A4
1
2
3
4
5
6
7
8
9
56 CEAB
55 CPAB
54 B0
53 GND
52 B1
51 B2
50 VCC
49 B3
48 B4
47 B5
46 GND
45 B6
44 B7
43 B8
MNA291
handbook, halfpage
VCC
data
input
to internal circuit
A5 10
GND 11
A6 12
A7 13
A8 14
Fig.2 Bus hold circuit.
162601
A9 15
A10 16
A11 17
GND 18
A12 19
A13 20
A14 21
VCC 22
A15 23
A16 24
GND 25
A17 26
OEBA 27
LEBA 28
MNA287
42 B9
41 B10
40 B11
39 GND
38 B12
37 B13
36 B14
35 VCC
34 B15
33 B16
32 GND
31 B17
30 CPBA
29 CEBA
Fig.1 Pin configuration.
1999 Oct 14
5
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