PCA9555
16-bit I
2
C-bus and SMBus I/O port with interrupt
Rev. 08 — 22 October 2009
Product data sheet
1. General description
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel
Input/Output (GPIO) expansion for I
2
C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I
2
C-bus I/O expanders. The improvements
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, and smaller packaging. I/O expanders provide a simple solution when
additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Output
and Polarity Inversion (active HIGH or active LOW operation) registers. The system
master can enable the I/Os as either inputs or outputs by writing to the I/O configuration
bits. The data for each Input or Output is kept in the corresponding Input or Output
register. The polarity of the read register can be inverted with the Polarity Inversion
register. All registers can be read by the system master. Although pin-to-pin and I
2
C-bus
address compatible with the PCF8575, software changes are required due to the
enhancements, and are discussed in
Application Note AN469.
The PCA9555 open-drain interrupt output is activated when any input state differs from its
corresponding input port register state and is used to indicate to the system master that
an input state has changed. The power-on reset sets the registers to their default values
and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus. The fixed I
2
C-bus address of the PCA9555 is
the same as the PCA9554, allowing up to eight of these devices in any combination to
share the same I
2
C-bus/SMBus.
2. Features
I
I
I
I
I
I
I
I
I
I
I
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
16 I/O pins which default to 16 inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
NXP Semiconductors
PCA9555
16-bit I
2
C-bus and SMBus I/O port with interrupt
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Six packages offered: DIP24, SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24
3. Ordering information
Table 1.
Ordering information
Name
PCA9555N
PCA9555D
PCA9555DB
DIP24
SO24
SSOP24
Description
plastic dual in-line package; 24 leads (600 mil)
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
×
4
×
0.85 mm
Version
SOT101-1
SOT137-1
SOT340-1
SOT355-1
SOT616-1
SOT994-1
Type number Package
PCA9555PW TSSOP24
PCA9555BS
PCA9555HF
HVQFN24
HWQFN24 plastic thermal enhanced very very thin quad flat
package; no leads; 24 terminals; body 4
×
4
×
0.75 mm
3.1 Ordering options
Table 2.
PCA9555N
PCA9555D
PCA9555DB
PCA9555PW
PCA9555BS
PCA9555HF
Ordering options
Topside mark
PCA9555
PCA9555D
PCA9555
PCA9555
9555
P55H
Temperature range
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
Type number
PCA9555_8
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
2 of 34
NXP Semiconductors
PCA9555
16-bit I
2
C-bus and SMBus I/O port with interrupt
4. Block diagram
PCA9555
8-bit
INPUT/
OUTPUT
PORTS
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
A0
A1
A2
write pulse
read pulse
I
2
C-BUS/SMBus
CONTROL
SCL
SDA
INPUT
FILTER
8-bit
INPUT/
OUTPUT
PORTS
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
DD
LP filter
INT
write pulse
read pulse
POWER-ON
RESET
V
DD
V
SS
002aac702
Remark:
All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCA9555
5. Pinning information
5.1 Pinning
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
002aac697
INT 1
A1 2
A2 3
IO0_0 4
IO0_1 5
IO0_2 6
IO0_3 7
IO0_4 8
IO0_5 9
IO0_6 10
IO0_7 11
V
SS
12
002aac698
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
PCA9555N
PCA9555D
IO0_6 10
IO0_7 11
V
SS
12
Fig 2.
PCA9555_8
Pin configuration for DIP24
Fig 3.
Pin configuration for SO24
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
3 of 34
NXP Semiconductors
PCA9555
16-bit I
2
C-bus and SMBus I/O port with interrupt
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
002aac699
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 A0
20 IO1_7
19 IO1_6
18 IO1_5
17 IO1_4
16 IO1_3
15 IO1_2
14 IO1_1
13 IO1_0
002aac700
PCA9555DB
PCA9555PW
IO0_6 10
IO0_7 11
V
SS
12
IO0_6 10
IO0_7 11
V
SS
12
Fig 4.
Pin configuration for SSOP24
20 SDA
19 SCL
21 V
DD
22 INT
Fig 5.
Pin configuration for TSSOP24
21 V
DD
20 SDA
19 SCL
18 A0
17 IO1_7
16 IO1_6
15 IO1_5
14 IO1_4
13 IO1_3
IO1_0 10
IO1_1 11
IO1_2 12
7
8
IO0_7
9
V
SS
002aac881
24 A2
1
2
3
4
5
6
IO0_6
24 A2
23 A1
terminal 1
index area
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
1
2
3
4
5
6
18 A0
17 IO1_7
16 IO1_6
15 IO1_5
14 IO1_4
13 IO1_3
IO1_0 10
IO1_1 11
IO1_2 12
7
8
9
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
PCA9555BS
PCA9555HF
IO0_6
IO0_7
V
SS
002aac701
Transparent top view
Transparent top view
Fig 6.
Pin configuration for HVQFN24
Fig 7.
Pin configuration for HWQFN24
PCA9555_8
23 A1
terminal 1
index area
22 INT
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
4 of 34
NXP Semiconductors
PCA9555
16-bit I
2
C-bus and SMBus I/O port with interrupt
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
DIP24, SO24,
SSOP24, TSSOP24
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
SS
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
A0
SCL
SDA
V
DD
[1]
Description
HVQFN24,
HWQFN24
22
23
24
1
2
3
4
5
6
7
8
9
[1]
10
11
12
13
14
15
16
17
18
19
20
21
address input 0
serial clock line
serial data line
supply voltage
supply ground
port 1 input/output
interrupt output (open-drain)
address input 1
address input 2
port 0 input/output
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HVQFN and HWQFN package die supply ground is connected to both the V
SS
pin and the exposed center
pad. The V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
PCA9555_8
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 — 22 October 2009
5 of 34
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