TC551001APL-70 datasheet, PDF - EEWORLD Datasheet

TC551001APL-70: DescriptionIC 128K X 8 STANDARD SRAM, 70 ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32, Static RAM; Categorystorage storage; File Size64KB，1 Pages; ManufacturerToshiba Semiconductor; Websitehttp://toshiba-semicon-storage.com/

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TC551001APL-70 Overview

IC 128K X 8 STANDARD SRAM, 70 ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32, Static RAM

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Toshiba Semiconductor
Parts packaging code	DIP
package instruction	DIP,
Contacts	32
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	70 ns
JESD-30 code	R-PDIP-T32
JESD-609 code	e0
length	42 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	4.8 mm
Minimum standby current	2 V
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

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