High Speed
KM416C254D
CMOS DRAM
High Speed 256K x 16Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 262,144 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access
of memory cells within the same row. Access time (-4), power consumption(Normal or Low power) and package type(SOJ or TSOP-II)
are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
Furthermore, Self-refresh operation is available in L-version. This 256Kx16 EDO Mode DRAM family is fabricated using Samsung′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
• Part Identification
- KM416C254D/DL (5V, 512 Ref.)
• Extended Data Out Mode operation
• 2 CAS Byte/Wrod Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL compatible inputs and outputs
•
Active Power Dissipation
Unit : mW
Speed
-4
Active Power Dissipation
990
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in 40-pin SOJ 400mil and 44(40)-pin
TSOP(II) 400mil packages
• Triple +5V±10% power supply
•
Refresh Cycles
Part
NO.
C254D
V
CC
5V
Refresh
cycle
512
Refresh period
Normal
8ms
L-ver
128ms
RAS
UCAS
LCAS
W
Control
Clocks
VBB Generator
Vcc
Vss
Lower
Data in
Buffer
Sense Amps & I/O
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
FUNCTIONAL BLOCK DIAGRAM
•
Perfomance Range
Speed
-4
Refresh Timer
Row Decoder
t
RAC
40ns
t
CAC
13ns
t
RC
69ns
t
HPC
17ns
DQ0
to
DQ7
Refresh Control
Refresh Counter
Row Address Buffer
A0~A8
Col. Address Buffer
Column Decoder
Memory Array
262,144 x16
Cells
OE
DQ8
to
DQ15
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
High Speed
KM416C254D
CMOS DRAM
PIN CONFIGURATION
(Top Views)
•KM416C254DJ
•KM416C254DT
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
N.C
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
N.C
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
(SOJ)
(TSOP-II)
Pin Name
A0 - A8
DQ0 - 15
V
SS
RAS
UCAS
LCAS
W
OE
V
CC
N.C
Pin Function
Address Inputs
Data In/Out
Ground
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Read/Write Input
Data Output Enable
Power(+5V)
No Connection
High Speed
KM416C254D
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN,
V
OUT
V
CC
Tstg
P
D
I
OS
Rating
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1.1
50
CMOS DRAM
Units
V
V
°C
W
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1.0
*1
0.8
Units
V
V
V
V
*1 : V
CC
+2.0V/20ns(5V), Pulse width is measured at V
CC
*2 : -2.0V/20ns(5V), Pulse width is measured at V
SS
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Input Leakage Current (Any input 0≤V
IN
≤V
IN
+0.5V,
all other input pins not under test=0 Volt)
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
OH
=-5mA)
Output Low Voltage Level(I
OL
=4.2mA)
Symbol
I
I(L)
I
O(L)
V
OH
V
OL
Min
-5
-5
2.4
-
Max
5
5
-
0.4
Units
uA
uA
V
V
High Speed
KM416C254D
DC AND OPERATING CHARACTERISTICS
(Continued)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
CC7
I
CCS
Power
Don′t care
Don′t care
Don′t care
Don′t care
Normal
L
Don′t care
L
L
Max
180
2
180
145
1
150
180
300
200
CMOS DRAM
Units
mA
mA
mA
mA
mA
uA
mA
uA
uA
I
CC1
* : Operating Current (RAS and UCAS, LCAS, Address cycling @
t
RC
=min.)
I
CC2
: Standby Current (RAS=UCAS=LCAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (UCAS=LCAS=V
IH
, RAS, Address cycling @
t
RC
=min.)
I
CC4
* : Extended Data Out Mode Current (RAS=V
IL
, UCAS or LCAS, Address cycling @
t
HPC
=min.)
I
CC5
: Standby Current (RAS=UCAS=LCAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @
t
RC
=min.)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, UCAS, LCAS=0.2V,
DQ=Don′t care, T
RC
=31.25us, T
RAS
=T
RAS
min~300ns
I
CCS
: Self Refresh Current
RAS=UCAS=LCAS=V
IL
, W=OE=A0 ~ A12(A11)=V
CC
-0.2V or 0.2V,
DQ0 ~ DQ15=V
CC
-0.2V, 0.2V or Open
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
, I
CC6
and I
CC7
, address can be changed maximum once while RAS=V
IL
. In
I
CC4
, address can be changed maximum once within one Hyper page mode cycle time,
t
HPC
.
High Speed
KM416C254D
CAPACITANCE
(T
A
=25°C, V
CC
=5V, f=1MHz)
Parameter
Input capacitance [A0 ~ A12]
Input capacitance [RAS, UCAS, LCAS, W, OE]
Output capacitance [DQ0 - DQ15]
Symbol
C
IN1
C
IN2
C
DQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤60°C,
See note 1,2)
Test condition : V
CC
=5.0V±10%, Vih/Vil=2.8/0.4V, Voh/Vol=2.0/0.8V
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command set-up time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Symbol
Min
-4
Max
ns
ns
40
13
20
3
3
2
25
40
9
34
6.5
18
13
5
0
8
0
6.5
20
0
0
0
0
7
7
8
6
10K
27
20
10K
11
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
8
8
7
13
13
4
10
3,4,10
3,4,5
3,10
3
6,12
2
Units
Notes
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
CEZ
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCS
t
WCH
t
WP
t
RWL
t
CWL
69
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