ICS8725I-01
1:5 D
IFFERENTIAL
-
TO
-HSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8725I-01 is a highly versatile 1:5 Differential-to-
HSTL Clock Generator. The ICS8725I-01 has a fully
integrated PLL and can be configured as zero delay buffer,
multiplier or divider, and has an output frequency range of
31.25MHz to 630MHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows
the device to achieve “zero delay” between the input clock
and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
F
EATURES
•
5 differential HSTL outputs
•
Selectable differential CLKx, nCLKx input pairs
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
•
Output frequency range: 31.25MHz to 630MHz
•
Input frequency range: 31.25MHz to 630MHz
•
VCO range: 250MHz to 630MHz
•
External feedback for “zero delay” clock regeneration
with configurable frequencies
•
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•
Static phase offset: 30ps ± 125ps
•
Cycle-to-cycle jitter: 35ps (maximum)
•
Output skew: 50ps (maximum)
•
3.3V core, 1.8V output operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
B
LOCK
D
IAGRAM
PLL_SEL
Q0
nQ0
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
,
÷64
Q1
nQ1
0
1
1
Q2
nQ2
Q3
nQ3
Q4
nQ4
P
IN
A
SSIGNMENT
PLL_SEL
SEL3
GND
V
DDO
V
DDA
nQ4
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
32 31 30 29 28 27 26 25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
DD
nFB_IN
FB_IN
SEL2
GND
nQ0
Q0
V
DDO
V
DD
Q4
0
24
23
22
21
20
19
18
17
V
DDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
DDO
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
ICS8725I-01
SEL0
SEL1
SEL2
SEL3
MR
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
www.idt.com
1
REV. A AUGUST 9, 2010
8725AYI-01
ICS8725I-01
1:5 D
IFFERENTIAL
-
TO
-HSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2,
12, 29
3
4
5
6
7
Name
SEL0, SEL1,
SEL2, SEL3
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Type
Input
Input
Input
Input
Input
Input
Description
Determines output divider values in Table 3.
Pulldown
LVCMOS/LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1.
Pulldown
When LOW, selects CLK0, nCLK0. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inver ted outputs nQx to go
Pulldown
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Core supply pins.
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
Power supply ground.
Differential output pair. HSTL interface levels.
Output supply pins.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
8
9, 32
10
11
13, 28
14, 15
16, 17,
24, 25
18, 19
20, 21
22, 23
26, 27
30
31
MR
V
DD
nFB_IN
FB_IN
GND
nQ0, Q0
V
DDO
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
V
DDA
PLL_SEL
Input
Power
Input
Input
Power
Output
Power
Output
Output
Output
Output
Power
Input
Pullup
NOTE:
Pullup
and
Pulldow
n refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8725AYI-01
www.idt.com
2
REV. A AUGUST9, 2010
ICS8725I-01
1:5 D
IFFERENTIAL
-
TO
-HSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference Frequency Range (MHz)*
250 - 630
125 - 315
62.5 - 157.5
31.25 - 78.75
250 - 630
125 - 315
62.5 - 157.5
250 - 630
125 - 315
250 - 630
125 - 315
62.5 - 157.5
31.25 - 78.75
62.5 - 157.5
31.25 - 78.75
31.25 - 78.75
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q4, nQ0:nQ4
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
*NOTE: VCO frequency range for all configurations above is 250MHz to 630MHz.
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
8725AYI-01
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
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3
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q4, nQ0:nQ4
÷4
÷4
÷4
÷8
÷8
÷8
÷ 16
÷ 16
÷ 32
÷ 64
÷2
÷2
÷4
÷1
÷2
÷1
REV. A AUGUST 9, 2010
ICS8725I-01
1:5 D
IFFERENTIAL
-
TO
-HSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
0
Test Conditions
Minimum
3.135
3.135
1. 6
Typical
3.3
3.3
1.8
Maximum
3.465
3.465
2. 0
137
17
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
PLL_SEL
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
PLL_SEL
V
DD
= V
IN
= 3.465V
V
DDO
= 2V
V
DD
= V
IN
= 3.465V
V
DDO
= 2V
V
DD
= 3.465V,
V
DDO
= 2V, V
IN
= 0V
V
DD
= 3.465V,
V
DDO
= 2V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
I
IH
I
IL
V
PP
Input
High Current
Input
Low Current
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
0.5
NOTE 1: For single ended applications, the maximum input voltage for CLKx, nCLKx is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
8725AYI-01
www.idt.com
4
REV. A AUGUST9, 2010
ICS8725I-01
1:5 D
IFFERENTIAL
-
TO
-HSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
4D. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
Output High Voltage;
V
OH
NOTE 1
Output Low Voltage;
V
OL
NOTE 1
V
OX
V
SWING
Output Crossover Voltage
Test Conditions
Minimum
1
0
40% x (V
OH
- V
OL
) + V
OL
0.6
Typical
Maximum
1.4
0.4
60% x (V
OH
- V
OL
) + V
OL
1.1
Units
V
V
V
V
Peak-to-Peak
Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to ground.
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
IN
Parameter
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
63 0
630
Units
MHz
MHz
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t(Ø)
t
sk(o)
t
jit(cc)
t
jit(Ø)
t
L
t
R
/ t
F
t
PW
Parameter
Output Frequency
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
Output Rise/Fall Time
Output Pulse Width
20% to 80%
300
t
PERIOD
/2 - 85
t
PERIOD
/2
PLL_SEL = 0V
IJ 630MHz
PLL_SEL = 3.3V
3.4
-95
3.9
30
Test Conditions
Minimum
Typical
Maximum
630
4. 5
155
50
35
±50
1
700
t
PERIOD
/2 + 85
Units
MHz
ns
ps
ps
ps
ps
ms
ps
ps
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal
across alll conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
8725AYI-01
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5
REV. A AUGUST 9, 2010
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