84330BY-03LFT datasheet, PDF - EEWORLD Datasheet

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84330BY-03LFT: DescriptionTQFP-32, Reel; CategoryThe embedded processor and controller Microcontrollers and processors; File Size546KB，24 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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84330BY-03LFT Overview

TQFP-32, Reel

84330BY-03LFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	LQFP,
Contacts	32
Manufacturer packaging code	PRG32
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G32
JESD-609 code	e3
length	7 mm
Humidity sensitivity level	3
Number of terminals	32
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	700 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	25 MHz
Maximum seat height	1.6 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

84330BY-03LFT Preview

700MHz, Low Jitter, Crystal-to-3.3V

Differential LVPECL Frequency Synthesizer

84330B-03

Data Sheet

General Description

The 84330B-03 is a general purpose, dual output high frequency

synthesizer. The VCO operates at a frequency range of 250MHz to

700MHz. The VCO and output frequency can be programmed using

the I

C interface. The output can be configured to divide the VCO

frequency by 1, 2, 3, 4, and 6.

Additionally, the device supports spread spectrum clocking (SSC) for

minimizing Electromagnetic Interference (EMI). The low cycle-cycle

jitter and broad frequency range of the 84330B-03 make it an ideal

clock generator for a variety of demanding applications which require

high performance.

Features

•

Fully integrated PLL, no external loop filter requirements

Two differential 3.3V LVPECL output pairs

Crystal oscillator interface: 10MHz to 25MHz

Output frequency range: 41.67MHz to 700MHz

VCO range: 250MHz to 700MHz

Parallel or I

C interface for programming M and N dividers during

power-up

Supports Spread Spectrum Clocking (SSC)

Center spread: selectable ±0.5%, ±1.0%, ±1.5%, ±2%

Up/Down spread: selectable ±0.5%, ±1.0%, ±1.5%, ±2%, 2.5%,

3.%, 3.5%, 4%

•

RMS period jitter: 9ps (maximum)

Cycle-to-cycle jitter: 40ps (maximum)

3.3V supply voltage

0°C to 70°C ambient operating temperature

Available in lead-free (RoHS 6) package

Block Diagram

Pullup

VCO_SEL

Pullup

XTAL_IN

XTAL_OUT

FREF_EXT

Pulldown

÷16

XTAL_SEL

Pullup

OSC

Pin Assignment

nQ0

nQ1

32 31 30 29 28 27 26 25

PLL

Phase Detector

SCL

SDA

ADDR_SEL

÷1

÷2

XTAL_OUT

10 11 12 13 14 15 16

nP_LOAD

VCO_SEL

VCO

÷M

÷2

nQ0

CCA

FREF_EXT

XTAL_SEL

÷2

÷3

÷4

÷6

ADR_SEL

Pulldown

S_DATA

S_CLOCK

nP_LOAD

Pullup

M0:M8

M0:M7 = Pulldown, M8 = Pullup

Pulldown

nQ1

XTAL_IN

C Parallel Interface

84330B-03

32 Lead LQFP

Y Package

7mm x 7mm x 1.4mm package body

Top View

Revision C January 15, 2016

84330B-03 Data Sheet

The 84330B-03 uses either a parallel interface or industry standard

C interface to control the programming of the internal dividers. The

power on defaults are summarized as follows:

Parallel Mode:

SSC Mode:

256

Off

Output

Q0/nQ0 output at 267MHz

(using a 16.667MHz crystal)

Q1/nQ1 output at 133MHz

(using a 16.667MHz crystal)

The programming mode is controlled by the nP_LOAD pin. When

this pin is low, The M, N values are set by the logic values on the M,

N pins. If nP_LOAD is HIGH, the M, N dividers can be changed

using the I

C serial programming interface.

The I

C control registers are defined below:

Data Byte 0

Control Bit

Power-up Default Value

Data Byte 1

Control Bit

Power-up Default Value

Not

Used

Not

Used

Not

Used

Not

Used

Not

Used

Data Byte 2

Control Bit

Power-up Default Value

Down

SSC5

SSC4

SSC3

SSC2

SSC1

SSC0

C A

DDRESSING

The 84330B-03 can be set to decode one of two addresses to

minimize the chance of address conflict on the I

C bus. The address

that is decoded is controlled by the setting of the ADDR_SEL pin

(pin 3).

ADDR_SEL (pin 3) = 0 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

ADDR_SEL (pin 3) = 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

Revision C January 15, 2016

84330B-03 Data Sheet

C Interface - Protocol

The 84330B-03 is a slave-only device and uses the standard I C

protocol as shown in the below diagrams. The maximum SCL

frequency is greater than 10MHz which is more than sufficient for

standard I

C clock speeds.

SCLK

SDATA

START

Valid Data

Acknowledge

STOP

START (ST)

- defined as high-to-low transition on SDA while holding

SCL HIGH.

DATA

- Between START and STOP cycles, SDA is synchronous with

SCL. Data may change only when SCL is LOW and must be stable

when SCL is HIGH.

ACKNOWLEDGE (AK)

- SDA is driven LOW before the SCL rising

edge and held LOW until the SCL falling edge.

STOP (SP)

- defined as low-to-high transition on SDA while holding

SCL HIGH.

Revision C January 15, 2016

84330B-03 Data Sheet

C Interface - A Write Example

A serial transfer to the 84330B-03 always consists of an address

cycle followed by 4 data bytes: 1 dummy byte followed by 3 data

bytes. Any additional bytes beyond the 4 data bytes will not be

acknowledged and the 84330B-03 will leave the data bus HIGH.

These extra bits will not be loaded into the serial control register.

1 Bit

Slave Address: 7 Bits

Refer to page 2 for address choices based on ADDR_SEL pin setting

Once the 4 Data bytes are loaded and the master generates a stop

condition, the values in the serial control register are latched into the

M divider, N divider, and control bits and the device will smoothly

slew to the new frequency and any changes to the state of the

control bits will take effect.

R/W

Dummy Byte 0: 8 Bits

1 Bit

Data Byte 0: 8 Bits

1 Bit

Data Byte 1: 8 Bits

Not Used

1 Bit

Data Byte 2: 8 Bits

Down

SSC5

SSC4

SSC3

SSC2

SSC1

SSC0

1 Bit

Data Byte values latched into control registers here.



Revision C January 15, 2016

84330B-03 Data Sheet

Spread Spectrum Operation

NOTE: The functional description that follows used a 16.6667MHz

crystal with an M divide value of 160.

Spread Spectrum operation is controlled by I

C Data Byte 2, Spread

Spectrum Control Register. Bits SSC0 – SSC5 (SS) of the register

are a subtrahend to the M-divider for down-spread, and they are an

addend and a subtrahend to the M-divider for center-spread. When

the UP bit is HIGH, then up-spread has been selected and the

M-divider value will toggle between the programmed M value, and

M+SS at a 32kHz rate. When the DN bit is HIGH, then down-spread

Table 1A. SS Mode Function Table

SSC7

SSC6

SS Mode

Off

Down-Spread

Up-Spread

Center-Spread

has been selected and the M-divider value will toggle between the

programmed M value, and M-SS at a 32kHz rate. When both the UP

and DN bits are HIGH, then center-spread has been selected and

the M-divider will toggle between M+SS and M-SS at a 32kHz rate.

The table below shows the desired SS value to achieve 0.5%, 1%

and 1.5% spread at selected VCO frequencies. To disable Spread

Spectrum operation, program both the UP and DN bits to LOW.

Spread Spectrum operation will also be disabled when the

nP_LOAD input is LOW.

Table 1B. Up/Down Spread Configuration

Up- or Down-Spread SS Value

SSC5

SSC4

SSC3

SSC2

SSC1

SSC0

Spread %

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

Table 1C. Center Spread Configuration

Center-Spread SS Value

SSC5

SSC4

SSC3

SSC2

SSC1

SSC0

Spread (±) %

0.50

1.00

1.50

2.00

Revision C January 15, 2016

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84330BY-03LFT Related Products

	84330BY-03LFT	84330BY-03LF
Description	TQFP-32, Reel	TQFP-32, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TQFP	TQFP
package instruction	LQFP,	LQFP,
Contacts	32	32
Manufacturer packaging code	PRG32	PRG32
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
JESD-30 code	S-PQFP-G32	S-PQFP-G32
JESD-609 code	e3	e3
length	7 mm	7 mm
Humidity sensitivity level	3	3
Number of terminals	32	32
Maximum operating temperature	70 °C	70 °C
Maximum output clock frequency	700 MHz	700 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	260	260
Master clock/crystal nominal frequency	25 MHz	25 MHz
Maximum seat height	1.6 mm	1.6 mm
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	7 mm	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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