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T2803-PLSW

Description
RF and Baseband Circuit, 7 X 7 MM, MO-220, QFN-48
CategoryWireless rf/communication    Telecom circuit   
File Size570KB,28 Pages
ManufacturerAtmel (Microchip)
Environmental Compliance  
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T2803-PLSW Overview

RF and Baseband Circuit, 7 X 7 MM, MO-220, QFN-48

T2803-PLSW Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAtmel (Microchip)
Parts packaging codeQFN
package instructionHVQCCN,
Contacts48
Reach Compliance Codecompliant
JESD-30 codeS-XQCC-N48
JESD-609 codee3
length7 mm
Humidity sensitivity level2
Number of functions1
Number of terminals48
Maximum operating temperature60 °C
Minimum operating temperature-10 °C
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1 mm
Nominal supply voltage3 V
surface mountYES
Telecom integrated circuit typesRF AND BASEBAND CIRCUIT
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width7 mm

T2803-PLSW Preview

Features
Supply-voltage Range 3V to 4.6V (Regulated)
Auxiliary Voltage Regulator On-chip (3.2V to 4.6V)
Low Current Consumption
Few Low-cost External Components
No Mechanical Tuning Required
Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz)
Fast Settling Synthesizer (864 kHz Channel Spacing)
TX Preamplifier with 3 dBm Output Power at 2.45 GHz (4 Programmable Power Levels)
Ramp-signal Generator for Power Ramping and Power Control of External SiGe Power
Amplifier (T7024 and T7026)
Electrostatic sensitive device.
Observe precautions for handling.
2.4 GHz
WDECT/ISM
Single-chip
Transceiver
T2803
Preliminary
1. Description
The T2803 is an RF IC for low-power applications in the 2.45 GHz ISM band. The
QFN48-packaged IC is a complete transceiver including image rejection mixer, IF
amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping
generator for power amplifiers, integrated synthesizer, fully integrated VCO and Gaus-
sian data filter for TX. No mechanical tuning is necessary in production.
Figure 1-1.
Block Diagram
MIXER
OUT IF_IN
IR MIXER
RF_IN
DEMOD
BB FILTER
RAMP_OUT
RAMP_SET
RAMP
GEN
RAMP
D/A
D/A
RSSI
DEMOD DAC
RSSI
IF AMP 1
DEMOD
IF_TANK
IF AMP 2
BB_OUT
TANK
CF
VCO
TX/RX
SWITCH
GF
TX_DATA
PC
TX_OUT
TX DRIVER
f
:n
PD
3-WIRE
BUS
CLOCK
DATA
ENABLE
VCO
REG
AUX
REG
CP
RC
f
:n
CTRL
LOGIC
RX_ON
TX_ON
PU_RX/TX
PU_PLL
VREG_VCO
VS_VCO
VREG
VS_REG
OLE
GND_VCO
PU_REG REG_CTRL VTUNE
CP
I_CPSW
LD
REF_CLK
Rev. 4572H–DECT–04/05
Table 1-1.
Name
AUX REG
BBF
CP
DAC
DEMOD
GF
IF AMP1
IF AMP2
IR MIXER
PC
PD
RAMP GEN
RC
RSSI
TX DRIVER
Functional Block Description
Description
Auxiliary voltage regulator
Baseband filter
Charge pump
D/A converter for demodulator tuning
Demodulator
Gaussian filter for transmit data
1st intermediate frequency amplifier
2nd intermediate frequency amplifier
Image rejection mixer
Programmable counter
Phase detector
Ramp-signal generator
Reference counter
Received signal-strength indicator
Buffer amplifier for TX_OUT
Switches VCO signal to IR MIXER respectively TX DRIVER
Voltage-controlled oscillator
Voltage regulator for VCO
TX/RX SWITCH
VCO
VCO REG
2. Pin Configuration
Figure 2-1.
Pinning QFN48
PU_PLL
TX_ON
RAMP_SET
PU_RX/TX
GND_PLL
TX_DATA
VS_MIXER
I_CPSW
RX_ON
48 47 46 45 44 43 42 41 40 39 38 37
CLOCK
DATA
ENABLE
REF_CLK
LD
PU_REG
VS_PLL
VREG
REG_CTRL
VS_REG
GND_CP
VS_CP
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
BB_CF
DEMOD_TANK2
GND_VCO
DEMOD_TANK1
VREG_VCO
REG_DEC
DAC_DEC
VS_VCO
BB_OUT
VTUNE
GND1
CP
OLE
36
35
34
33
32
31
RAMP_OUT
IF_IN2
IF_IN1
VS_IF
TX_OUT
GND3
RF_IN2
RF_IN1
GND2
IF_TANK2
IF_TANK1
RSSI
T2803
30
29
28
27
26
25
2
T2803 [Preliminary]
4572H–DECT–04/05
T2803 [Preliminary]
Table 2-1.
Pin
Pin Description
Symbol
Function
Configuration
VS_PLL
1
CLOCK
3-wire-bus: Clock input
7
2
DATA
3-wire-bus: Data input
CLOCK
DATA
ENABLE
1,2,3
5k
5k
3
ENABLE
3-wire-bus: Enable input
GND_PLL
43
VS_PLL
7
4
REF_CLK
Reference-frequency input
REF_CLK
4
10k
10k
GND_PLL
43
LD
5
100
5
LD
Lock-detect output
GND_PLL
43
PU_REG
6
6
PU_REG
Power-up input for auxiliary voltage regulator
25k
25k
GND_PLL
43
3
4572H–DECT–04/05
Table 2-1.
Pin
Pin Description (Continued)
Symbol
Function
Configuration
VS_PLL
7
GND1
VS_REG
10
VS_CP
12
VS_VCO
14
18
GND2
28
7
VS_PLL
PLL supply voltage
VS_IF
33
GND3
31
GND_VCO
16
GND_CP
11
VS_MIXER
42
GND_PLL
43
VS_REG
10
VS_PLL
7
REG_CTRL
9
VREG
8
8
VREG
Auxiliary voltage-regulator output
9
REG_CTRL
Auxiliary voltage-regulator control output
10
VS_REG
Auxiliary voltage-regulator supply voltage
GND_PLL
43
VS_CP
12
11
12
13
GND_CP
VS_CP
CP
Charge-pump ground
Charge-pump supply voltage
Charge-pump output
VS_PLL
7
CP
13
GND_PLL
43
GND_CP
11
4
T2803 [Preliminary]
4572H–DECT–04/05
T2803 [Preliminary]
Table 2-1.
Pin
Pin Description (Continued)
Symbol
Function
Configuration
VS_VCO
14
14
15
16
VS_VCO
VREG_VCO
GND_VCO
VCO voltage-regulator supply voltage
VCO voltage-regulator control output
VCO ground
VS_PLL
7
VREG_VCO
15
GND_PLL
43
GND_VCO
16
VREG_VCO
15
VS_PLL
7
17
VTUNE
VCO tuning voltage input
VTUNE
17
GND_PLL
43
GND_VCO
16
VS_PLL
7
GND1
VS_REG
10
VS_CP
12
VS_VCO
14
GND3
18
GND2
28
18
GND1
Ground
VS_IF
33
31
GND_VCO
16
GND_CP
11
VS_MIXER
42
GND_PLL
43
5
4572H–DECT–04/05
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