841S01CGLF datasheet, PDF - EEWORLD Datasheet

EEWORLDEEWORLD

Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 841S01CGLF

Preview

841S01CGLF: DescriptionTSSOP-16, Tube; CategoryThe embedded processor and controller Microcontrollers and processors; File Size440KB，18 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

Download Datasheet Parametric View All

841S01CGLF Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	841S01CGLF	-	-	View	Buy Now

841S01CGLF Overview

TSSOP-16, Tube

841S01CGLF Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP16,.25
Contacts	16
Manufacturer packaging code	PGG16
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	TSSOP 4.4 MM 0.65MM PITCH
JESD-30 code	R-PDSO-G16
JESD-609 code	e3
length	5 mm
Humidity sensitivity level	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	100 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Master clock/crystal nominal frequency	25 MHz
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum slew rate	80 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

841S01CGLF Preview

PCI ExpressTM Clock Generator

841S01

DATA SHEET

General Description

The 841S01 is a PLL-based clock generator specifically designed for

PCI_Express™ Clock Generation applications. This device

generates a 100MHz HCSL clock. The device offers a HCSL (Host

Clock Signal Level) clock output from a clock input reference of

25MHz. The input reference may be derived from an external source

or by the addition of a 25MHz crystal to the on-chip crystal oscillator.

An external reference may be applied to the XTAL_IN pin with the

XTAL_OUT pin left floating.

The device offers spread spectrum clock output for reduced EMI

applications. An I

2

C bus interface is used to enable or disable spread

spectrum operation as well as select either a down spread value of

-0.35% or -0.5%.

Features

•

One 0.7V current mode differential HCSL output pair

Crystal oscillator interface: 25MHz

Output frequency: 100MHz

RMS period jitter: 3ps (maximum)

Cycle-to-cycle jitter: 35ps (maximum)

I

2

C support with readback capabilities up to 400kHz

Spread Spectrum for electromagnetic interference (EMI) reduction

3.3V operating supply mode

0°C to 70°C ambient operating temperature

Available in lead-free (RoHS 6) package

Block Diagram

25MHz

Pin Assignment

PLL

Divider

Network

SRCT0

SRCC0

V

SS

V

DD

SRCT0

SRCC0

V

DD

V

SS

IREF

V

SS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

DD

SDATA

SCLK

XTAL_OUT

XTAL_IN

V

DD

V

SS

V

DDA

XTAL_IN

OSC

XTAL_OUT

SDATA

Pullup

SCLK

Pullup

I

2

C

Logic

IREF

841S01

16-Lead TSSOP

5mm x 4.4mm x 0.925mm package body

G Package

Top View

841S01 Rev B 11/16/15

1

841S01 DATA SHEET

Table 1. Pin Descriptions

Number

1, 6, 8, 10

2, 5, 11, 16

3, 4

7

9

12,

13

14

15

Name

V

SS

V

DD

SRCT0, SRCC0

IREF

V

DDA

XTAL_IN,

XTAL_OUT

SCLK

SDATA

Type

Power

Output

Input

Power

Input

I/O

Pullup

Description

Ground for core and SRC outputs.

Power supply for core and SRC outputs.

Differential output pair. HCSL interface levels.

An external fixed precision resistor (475



) from this pin to ground provides a

reference current used for differential current-mode SRCCx, SRCTx clock

outputs.

Analog supply pin.

Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.

I

2

C SMBus compatible SCLK. This pin has an internal pullup resistor, but is in

high-impedance in power-down mode. LVCMOS/LVTTL interface levels.

I

2

C SMBus compatible SDATA. This pin has an internal pullup resistor, but is

in high-impedance in power-down mode. LVCMOS/LVTTL interface levels.

NOTE:

Pullup

refers to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

C

IN

R

PULLUP

Parameter

Input Capacitance

Input Pullup Resistor

Test Conditions

Minimum

Typical

4

51

Maximum

Units

pF

k



Rev B 11/16/15

2

PCI EXPRESSTM CLOCK GENERATOR

841S01 DATA SHEET

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer, a

two-signal serial interface is provided. Through the Serial Data

Interface, various device functions, such as individual clock output

buffers, can be individually enabled or disabled. The registers

associated with the Serial Data Interface initialize to their default

setting upon power-up, and therefore, use of this interface is optional.

Clock device register changes are normally made upon system

initialization, if any are required. The interface cannot be used during

system operation for power management functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read, block

write, and block read operations from the controller. For block

write/read operation, the bytes must be accessed in sequential order

from lowest to highest byte (most significant bit first) with the ability to

stop after any complete byte has been transferred. For byte write and

byte read operations, the system controller can access individually

indexed bytes. The offset of the indexed byte is encoded in the

command code, as described in

Table 3A.

The block write and block read protocol is outlined in

Table 3B,

while

Table 3C

outlines the corresponding byte write and byte read

protocol. The slave receiver address is 11010010 (D2h).

Table 3A.Command Code Definition

Bit

7

6:5

4:0

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation.

Chip select address, set to “00” to access device.

Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.

Table 3B. Block Read and Block Write Protocol

Bit

1

2:8

9

10

11:18

19

20:27

28

29:36

37

38:45

46

Description = Block Write

Start

Slave address - 7 bits

Write

Acknowledge from slave

Command Code - 8 bits

Acknowledge from slave

Byte Count - 8 bits

Acknowledge from slave

Data byte 1 - 8 bits

Acknowledge from slave

Data byte 2 - 8 bits

Acknowledge from slave

Data Byte/Slave Acknowledges

Data Byte N - 8 bits

Acknowledge from slave

Stop

Bit

1

2:8

9

10