PCA9515AD-T datasheet, PDF - EEWORLD Datasheet

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PCA9515AD-T: DescriptionI2C-bus repeater - I2C-bus: 400 kHz; Inputs: 1 ; Operating temperature: -40~85 Cel; Operating voltage: 2.3~3.6 VDC; Outputs: 1; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size94KB，18 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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PCA9515AD-T Overview

I2C-bus repeater - I2C-bus: 400 kHz; Inputs: 1 ; Operating temperature: -40~85 Cel; Operating voltage: 2.3~3.6 VDC; Outputs: 1

PCA9515AD-T Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-06-14 00:00:00
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Maker	NXP
package instruction	PLASTIC, SO-8
Reach Compliance Code	unknown
Differential output	NO
Number of drives	2
Input properties	STANDARD
Interface integrated circuit type	LINE TRANSCEIVER
Interface standards	GENERAL PURPOSE
JESD-30 code	R-PDSO-G8
JESD-609 code	e4
length	4.9 mm
Number of functions	2
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	2.5/3.3 V
Certification status	Not Qualified
Maximum receive delay	120 ns
Number of receiver bits	2
Maximum seat height	1.75 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
maximum transmission delay	120 ns
width	3.9 mm

PCA9515AD-T Preview

PCA9515A

C-bus repeater

Rev. 04 — 11 April 2008

Product data sheet

1. General description

The PCA9515A is a CMOS integrated circuit intended for application in I

C-bus and

SMBus systems.

While retaining all the operating modes and features of the I

C-bus system, it permits

extension of the I

C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus

enabling two buses of 400 pF.

The I

C-bus capacitance limit of 400 pF restricts the number of devices and bus length.

Using the PCA9515A enables the system designer to isolate two halves of a bus, thus

more devices or longer length can be accommodated. It can also be used to run two

buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the

100 kHz bus is isolated when 400 kHz operation of the other is required.

Two or more

PCA9515As

cannot be put in series.

The PCA9515A design does not

allow this conﬁguration. Since there is no direction pin, slightly different ‘legal’ low voltage

levels are used to avoid lock-up conditions between the input and the output. A ‘regular

LOW’ applied at the input of a PCA9515A will be propagated as a ‘buffered LOW’ with a

slightly higher value. When this ‘buffered LOW’ is applied to another PCA9515A,

PCA9516A or PCA9518/A in series, the second PCA9515A, PCA9516A or PCA9518/A

will not recognize it as a ‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again.

The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, PCA9514/A cannot be used in

series with the PCA9515A, PCA9516A or PCA9518/A, but can be used in series with

themselves since they use shifting instead of static offsets to avoid lock-up conditions.

The output pull-down of each internal buffer is set for approximately 0.5 V, while the input

threshold of each internal buffer is set about 0.07 V lower, when the output is internally

driven LOW. This prevents a lock-up condition from occurring.

2. Features

2-channel, bidirectional buffer

C-bus and SMBus compatible

Active HIGH repeater enable input

Open-drain input/outputs

Lock-up free operation

Supports arbitration and clock stretching across the repeater

Accommodates Standard-mode and Fast-mode I

C-bus devices and multiple masters

Powered-off high-impedance I

C-bus pins

Operating supply voltage range of 2.3 V to 3.6 V

5.5 V tolerant I

C-bus and enable pins

NXP Semiconductors

PCA9515A

C-bus repeater

0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be

less than 400 kHz because of the delays added by the repeater)

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: SO8 and TSSOP8 (MSOP8)

3. Ordering information

Table 1.

Ordering information

amb

−

C to +85

Type number

PCA9515AD

PCA9515ADP

Topside

mark

PA9515A

9515A

Package

Name

SO8

TSSOP8

[1]

Description

plastic small outline package; 8 leads; body width 3.9 mm

plastic thin shrink small outline package; 8 leads;

body width 3 mm

Version

SOT96-1

SOT505-1

[1]

Also known as MSOP8.

4. Functional diagram

PCA9515A

SDA0

SDA1

SCL0

SCL1

pull-up

resistor

002aad738

GND

Fig 1.

Functional diagram of PCA9515A

PCA9515A_4

Product data sheet

Rev. 04 — 11 April 2008

2 of 18

NXP Semiconductors

PCA9515A

C-bus repeater

5. Pinning information

5.1 Pinning

n.c.

SCL0

SDA0

GND

SCL1

SDA1

n.c.

SCL0

SDA0

GND

002aad737

SCL1

SDA1

PCA9515AD

002aad736

PCA9515ADP

Fig 2.

Pin conﬁguration for SO8

Fig 3.

Pin conﬁguration for TSSOP8

(MSOP8)

5.2 Pin description

Table 2.

Symbol

n.c.

SCL0

SDA0

GND

SDA1

SCL1

Pin description

Description

not connected

serial clock bus 0; open-drain 5 V tolerant I/O

serial data bus 0; open-drain 5 V tolerant I/O

supply ground (0 V)

active HIGH repeater enable input (internal pull-up with 100 kΩ)

serial data bus 1; open-drain 5 V tolerant I/O

serial clock bus 1; open-drain 5 V tolerant I/O

supply voltage

PCA9515A_4

Product data sheet

Rev. 04 — 11 April 2008

3 of 18

NXP Semiconductors

PCA9515A

C-bus repeater

6. Functional description

Refer to

Figure 1 “Functional diagram of PCA9515A”.

The PCA9515A integrated circuit contains two identical buffer circuits which enable

C-bus and similar bus systems to be extended without degradation of system

performance.

The PCA9515A contains two bidirectional, open-drain buffers speciﬁcally designed to

support the standard LOW-level contention arbitration of the I

C-bus. Except during

arbitration or clock stretching, the PCA9515A acts like a pair of non-inverting, open-drain

buffers, one for SDA and one for SCL.

6.1 Enable

The EN pin is active HIGH with an internal pull-up and allows the user to select when the

repeater is active. This can be used to isolate a badly behaved slave on power-up until

after the system power-up reset. It should never change state during an I

C-bus operation

because disabling during a bus operation will hang the bus and enabling part way through

a bus cycle could confuse the I

C-bus parts being enabled.

The enable pin should only change state when the global bus and the repeater port are in

an idle state to prevent system failures.

6.2 I

C-bus systems

As with the standard I

C-bus system, pull-up resistors are required to provide the logic

HIGH levels on the buffered bus (standard open-collector conﬁguration of the I

C-bus).

The size of these pull-up resistors depends on the system, but each side of the repeater

must have a pull-up resistor. This part designed to work with Standard-mode and

Fast-mode I

C-bus devices in addition to SMBus devices. Standard-mode I

C-bus devices

only specify 3 mA output drive; this limits the termination current to 3 mA in a generic

C-bus system where Standard-mode devices and multiple masters are possible. Under

certain conditions higher termination currents can be used.

Please see Application Note

AN255, I

C/SMBus Repeaters, Hubs and Expanders

for

additional information on sizing resistors and precautions when using more than one

PCA9515A/PCA9516A in a system or using the PCA9515A/PCA9516A in conjunction

with the P82B96.

PCA9515A_4

Product data sheet

Rev. 04 — 11 April 2008

4 of 18

NXP Semiconductors

PCA9515A

C-bus repeater

7. Application design-in information

A typical application is shown in

Figure 4.

In this example, the system master is running

on a 3.3 V I

C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz

unless the slave bus is isolated and then the master bus can run at 400 kHz. Master

devices can be placed on either bus.

3.3 V

10 kΩ

SDA

SCL

BUS

MASTER

400 kHz

SDA0

SCL0

SDA1

SCL1

SDA

SCL

SLAVE

100 kHz

PCA9515A

bus 0

bus 1

002aad739

Fig 4.

Typical application

The PCA9515A is 5 V tolerant, so it does not require any additional circuitry to translate

between the different bus voltages.

When one side of the PCA9515A is pulled LOW by a device on the I

C-bus, a CMOS

hysteresis type input detects the falling edge and causes the internal driver on the other

side to turn on, thus causing the other side to also go LOW. The side driven LOW by the

PCA9515A will typically be at V

= 0.5 V.

In order to illustrate what would be seen in a typical application, refer to

Figure 5

and

Figure 6.

If the bus master in

Figure 4

were to write to the slave through the PCA9515A,

we would see the waveform shown in

Figure 5

on bus 0. This looks like a normal I

C-bus

transmission until the falling edge of the 8

clock pulse. At that point, the master releases

the data line (SDA) while the slave pulls it LOW through the PCA9515A. Because the V

of the PCA9515A is typically round 0.5 V, a step in the SDA will be seen. After the master

has transmitted the 9

clock pulse, the slave releases the data line.

On the bus 1 side of the PCA9515A, the clock and data lines would have a positive offset

from ground equal to the V

of the PCA9515A. After the 8

clock pulse the data line will

be pulled to the V

of the slave device, which is very close to ground in this example. It is

important to note that any arbitration or clock stretching events on bus 1 require that the

of the PCA9515A (see V

−V

ILc

Section 9 “Static characteristics”)

to be recognized

by the PCA9515A and then transmitted to bus 0.

PCA9515A_4

Product data sheet

Rev. 04 — 11 April 2008

5 of 18

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