X24026YG datasheet, PDF - EEWORLD Datasheet

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X24026YG: DescriptionEEPROM, 256X8, Serial, CMOS, ROHS COMPLIANT, SMART CARD-8; Categorystorage storage; File Size253KB，15 Pages; ManufacturerIC Microsystems Sdn Bhd; Environmental Compliance

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X24026YG Overview

EEPROM, 256X8, Serial, CMOS, ROHS COMPLIANT, SMART CARD-8

X24026YG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IC Microsystems Sdn Bhd
Parts packaging code	CARD
package instruction	,
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum clock frequency (fCLK)	0.1 MHz
JESD-30 code	R-XXMA-X8
memory density	2048 bit
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	8
word count	256 words
character code	256
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256X8
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Serial bus type	I2C
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	UNSPECIFIED
Terminal location	UNSPECIFIED
Maximum time at peak reflow temperature	NOT SPECIFIED
Maximum write cycle time (tWC)	10 ms

X24026YG Preview

This X24026 device has been acquired by

IC MICROSYSTEMS from Xicor, Inc.

ICmic

IC MICROSYSTEMS

X24026

Serial E2PROM

DESCRIPTION

256 x 8 Bit

FEATURES

•2.7V to 5.5V Power Supply

•Low Power CMOS

—Active Current Less Than 1mA

—Standby Current Less Than 50µA

•Internally Organized 256 x 8

•Self Timed Write Cycle

—Typical Write Cycle Time of 5 ms

•2 Wire Serial Interface

—Bidirectional Data Transfer Protocol

•Four Byte Page Write Operation

—Minimizes Total Write Time Per Byte

•High Reliability

—Endurance: 100,000 Cycles

—Data Retention: 100 Years

The X24026 is a CMOS 2048 bit serial E PROM, internally

organized 256 x 8. The X24026 features a serial

interface and software protocol allowing operation on a

simple two wire bus.

Xicor E PROMs are designed and tested for applications

requiring extended endurance. Inherent data retention is

greater than 100 years. Available in DICE form with ISO

7816 compatible pin out.

—ESD Protection > 2KV

FUNCTIONAL DIAGRAM

START CYCLE

SDA

START

STOP

H.V. GENERATION

TIMING

& CONTROL

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

SCL

+COMPARATOR

LOAD

INC

XDEC

E PROM

64 X 32

WORD

ADDRESS

COUNTER

R/W

YDEC

DATA REGISTER

OUT

ACK

7020 FRM 01

∧Xicor,

Inc. 1994, 1995, 1996 Patents

Pending 7020-1.2 2/24/97 T1/C0/D2 SH

Characteristics subject to change without notice

X24026

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the

device.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and out

of the device. It is an open drain output and may be

wire-ORed with any number of open drain or open

collector outputs.

An open drain output requires the use of a pull-up

resistor. For selecting typical values, refer to the

Guidelines for Calculating Typical Values of Bus Pull-Up

Resistors graph.

SDA

DIE CONFIGURATION

SCL

SDA

X24026 Die Revision

A .055 x .079

7020 FRM 02

PIN DESCRIPTIONS

Symbol

SDA

SCL

Description

Serial Data

Serial Clock

Ground

+5V

7020 FRM T01

X24026

DEVICE OPERATION

The X24026 supports a bidirectional bus oriented proto- col.

The protocol defines any device that sends data onto

the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is a master

and the device being controlled is the slave. The master will

always initiate data transfers and provide the clock for

both transmit and receive operations. Therefore, the

X24026 will be considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved

for indicating start and stop conditions. Refer to Figures 1 and

Start Condition

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH.

The X24026 continuously monitors the SDA and SCL lines

for the start condition and will not respond to any

command until this condition has been met.

Figure 1. Data Validity

SCL

SDA

DATA STABLE

DATA

CHANGE

7020 FRM 03

X24026

The X24026 will respond with an acknowledge after rec-

ognition of a start condition and its slave address. If both

the device and a write operation have been selected, the

X24026 will respond with an acknowledge after the

receipt of each subsequent eight bit word.

In the read mode the X24026 will transmit eight bits of data,

release the SDA line and monitor the line for an

acknowledge. If an acknowledge is detected and no stop

condition is generated by the master, the X24026 will

continue to transmit data. If an acknowledge is not

detected, the X24026 will terminate further data trans-

missions. The master must then issue a stop condition to

return the X24026 to the standby power mode and place

the device into a known state

Stop Condition

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used by the

X24026 to place the device in the standby power mode

after a read sequence. A stop condition can only be

issued after the transmitting device has released the bus.

Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting

eight bits. During the ninth clock cycle the receiver will

pull the SDA line LOW to acknowledge that it received the

eight bits of data. Refer to Figure 3.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

7020 FRM 04

Figure 3. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

7020 FRM 05

X24026

DEVICE ADDRESSING

Following a start condition the master must output the

address of the slave it is accessing. The most significant

four bits of the slave are the device type identifier (see Figure

4). For the X24026 this is fixed as 1010[B].

Following the start condition, the X24026 monitors the

SDA bus comparing the slave address being transmitted

with its slave address. Upon a correct compare the

X24026 outputs an acknowledge on the SDA line.

Depending on the state of the R/W bit, the X24026 will

execute a read or write operation.

WRITE OPERATIONS

Byte Write

For a write operation, the X24026 requires a second

address field. This address field is the word address,

R/W

Figure 4. Slave Address

DEVICE TYPE

IDENTIFIER

comprised of eight bits, providing access to any one of the

256 words of memory. Upon receipt of the word

address the X24026 responds with an acknowledge, and

awaits the next eight bits of data, again responding with

RESERVE

ADDRESS

BITS

7020 FRM 06

an acknowledge. The master then terminates the transfer by

generating a stop condition, at which time the X24026

begins the internal write cycle to the nonvolatile memory.

While the internal write cycle is in progress the X24026

inputs are disabled, and the device will not respond to

any requests from the master. Refer to Figure 5 for the

address, acknowledge and data transfer sequence.

The next three significant bits are reserved address bits.

The last bit of the slave address defines the operation to be

performed. When set to one a read operation is

selected, when set to zero a write operations is selected

Figure 5. Byte Write

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

WORD

ADDRESS

DATA

SDA LINE

BUS ACTIVITY:

X24026

7020 FRM 07

Figure 6. Page Write

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

WORD

ADDRESS (n)

DATA n

DATA n+1

DATA n+3

SDA LINE

BUS ACTIVITY:

X24026

NOTE: In this example n = xxxx 000 (B); x = 1 or 0

7020 FRM 08

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