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Datasheet> All Categories > logic> logic> PI74LVC109AL
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PI74LVC109AL

Description
J-Kbar Flip-Flop, LVC/LCX/Z Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, 0.173 INCH, PLASTIC, TSSOP-16
Categorylogic    logic   
File Size185KB，8 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Download Datasheet Parametric View All

PI74LVC109AL Overview

J-Kbar Flip-Flop, LVC/LCX/Z Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, 0.173 INCH, PLASTIC, TSSOP-16

PI74LVC109AL Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP16,.25
Contacts16
Reach Compliance Codecompliant
ECCN codeEAR99
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeJ-KBAR FLIP-FLOP
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTUBE
Peak Reflow Temperature (Celsius)235
power supply3.3 V
Prop。Delay @ Nom-Sup7.5 ns
propagation delay (tpd)9 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.65 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width4.4 mm

PI74LVC109AL Preview

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PI74LVC109A
Fast CMOS 3.3V Dual
J-K Flip-Flop
Product Features
• Functionally compatible with LCX family of products
• 1.65V - 3.6V V
CC
supply operation, –40°C to 85°C
• ESD Protection exceeds 2000V, Human Body Model
200V, Machine Model
• Inputs and Outputs are 5V I/O Tolerant
• Balanced sink and source output drives (24mA)
• Low ground bounce outputs, <0.8V @ 3.3V, 25°C
• Packages available:
– 16-pin 173-mil wide plastic TSSOP (L)
– 16-pin 150-mil wide plastic SOIC (W)
Product Description
Pericom Semiconductor’s PI74LVC series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving high speed while maintaining low power
operation.
The PI74LVC109A, a dual J-K flip-flop with set, reset, and positive-
edge trigger, features individual J, K inputs, clock (CP) inputs, set
(S
D
) and reset (R
D
) inputs; also complementary Q and Q outputs
The set and reset are asynchronous active low inputs and operate
independently of the clock input. The J and K inputs control the
state changes of the flip-flops as described in the function table.
The J and K inputs must be stable one setup time prior to the low-
to-high clock transition for predictable operation. The J-K design
allows operation as a D-type flip-flop by tying the J and K inputs
together..
Inputs can be driven from either 3.3V or 5.0V devices allowing the
PI74LVC109A to be used as a translator in a mixed 3.3V/5.0V system.
Functional Diagram
1
S
D
Pin Configuration
16
15
14
5
2
1
J
1
R
D
S
D
J
Q
FF1
Q
K
R
D
1
Q
1
Q
1
2
3
4
5
6
7
8
V
CC
2
R
D
2
J
2
K
2
CP
2
S
D
2
Q
2
Q
1
J
6
1
K
1
CP
4
1
CP
CP
16-Pin
L, W
13
12
11
10
9
7
3
1
K
1
S
D
1
Q
1
Q
1
1
R
D
GND
2
S
D
11
14
2
J
S
D
J
Q
FF2
Q
K
R
D
2
Q
2
Q
10
12
2
CP
CP
9
13
2
K
15
2
R
D
1
PS8678
03/20/03
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PI74LVC109A
Fast CMOS 3.3V
Dual J-K Flip-Flop
Truth Table
Inputs
Ope rating M ode s
Asynchronous Set
Asynchonous Reset
Undetermined
Toggle
Load "0" (Reset)
Load "1" (Set)
Hold "No Change"
Note:
1. H
h
L
I
X
↑
Q
O
Q
O
X
S
D
X
R
D
X
CP
X
J
X
K
X
Q
Outputs
X
Q
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
↑
↑
↑
↑
X
X
X
h
l
h
l
X
X
X
l
l
h
h
H
L
H
Q
0
L
H
Q
0
L
H
H
Q
0
H
L
Q
0
=
=
=
=
=
=
=
=
HIGH voltage level
HIGH voltage level of input set-up time prior to the LOW-to-HIGH CP transition
LOW voltage level
LOW voltage level of input set-up time prior to the LOW-to-HIGH CP transition
Don’t care
LOW-to-HIGH CP Transition
Level of Q before the indicated steady-state input conditions were established
Complement of Q or level of Q before the indicated steady-state input conditons were established
Pin Description
Pin Name s
X
CP
X
R
D
X
S
D
X
J,
X
K
X
Q
X
Q
De s cription
Clock Inputs, LOW- to- HIGH, edge- triggered
Asynchronous Reset Input (Active LOW)
Asynchronous Set Input (Active LOW)
Synchronous Inputs
True Flip- Flop Outputs
Complement Flip- Flop Outputs
Functional Block Diagram
Q
K
c
c
c
c
Q
J
c
c
c
c
S
D
R
D
c
c
CP
2
PS8678
03/20/03
Notes:
4. All unused inputs must be held at V
CC
or GND to ensure proper device operation.
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVC109A
Fast CMOS 3.3V
Dual J-K Flip-Flop
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, V
CC
............................................................ –0.5V to 6.5V
Input voltage range, V
I(1)
............................................................... –0.5V to 6.5V
Output voltage range V
O(1,2)
............................................... –0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ................................................................ –50mA
Output clamp current, I
OK
(V
O
<0) ........................................................... –50mA
Continuous output current, I
O
................................................................ ±50mA
Continuous current through V
CC
or GND .............................................. ±100mA
Package thermal impedance,
θ
JA
(3)
: W package ................................... 111°C/W
L package ....................................... 90°C/W
Storage Temperature range, T
stg .................................................................
–65°C to 150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other con-
ditions above those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for
extended periods may affect reliability.
Notes:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current rating are observed.
2. The value of V
CC
is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions
(4)
Parame te r
V
C C
V
IH
D e s cription
Supply Voltage
High- level Input Voltage
Condition
O perating
Data retention only
V
C C
= 1.65V to 1.95V
V
C C
= 2.3V to 2.7V
V
C C
= 2.7V to 3.6V
V
IL
Low- level Input Voltage
V
C C
= 1.65V to 1.95V
V
C C
= 2.3V to 2.7V
V
C C
= 2.7V to 3.6V
V
I
V
O
I
O H
Input Voltage
O utput Voltage
High- level output current
V
C C
= 1.65V
V
C C
= 2.3V
V
C C
= 2.7V
V
C C
= 3V
I
O L
Low- level output current
V
C C
= 1.65V
V
C C
= 2.3V
V
C C
= 2.7V
V
C C
= 3V
∆
t/
∆V
T
A
Input transition rise or fall rate
O perating free- air temperature
–40
0
0
M in.
1.65
1.5
0.65 x V
C C
1.7
2.0
0.35 x V
C C
0.7
0.8
5.5
V
C C
–4
–8
– 12
– 24
4
8
12
24
10
85
mA
V
M a x.
3.6
Units
ns/V
°C
3
PS8678
03/20/03
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PI74LVC109A
Fast CMOS 3.3V
Dual J-K Flip-Flop
DC Electrical Characteristics
(Over Recommended Operating Free-Air Temperature Range, unless otherwise noted)
Parame te rs
V
O H
Te s t Conditions
I
O H
= –100
µA
I
O H
= –4mA
I
O H
= –8mA
I
O H
= –12mA
I
O H
= –24mA
V
O L
I
O L
= 100µA
I
O L
= 4mA
I
O L
= 8mA
I
O L
= 12mA
I
O L
= 24mA
V
IK
I
I
I
O F F
I
C C
∆I
C C
C
I
I
IN
= –18mA
V
I
= 5.5V or GND
V
IN
or V
O
≤
5.5V
V
I
= V
C C
or GND,
I
O
= 0
One input a V
C C
–0.6V,
Other inputs at V
C C
or GND
V
I
= V
C C
or GND
V
CC
1.65V to 3.6V
1.65V
2.3V
2.7V
3V
3V
1.65V to 3.6V
1.65V
2.3V
2.7V
3V
2.3V
3.6V
0V
3.6V
2.7V to 3.6V
3.3V
3
–0 . 7
M in.
V
C C
–0.2V
1. 2
1. 7
2.2
2.4
2.2
0.2
0.45
0.7
0.4
0.55
–1.2
±5
±10
10
500
pF
µA
V
Typ.†
M a x.
Units
†
All typical values are measured at V
CC
= 3.3V, T
A
= 25°C.
Switching Characteristics
Symbol
t
P LH,
t
P HL
t
P LH
t
P HL
t
S U
t
H
t
REM
t
W
t
W
t
S K (0)
(Over recommended operating free-air temperature range,unless otherwise noted, see Figures 1through 3)
V
CC
= 2.5V ±0.2V
Parame te r
Propagation Delay,
X
CP to
X
Q or
X
Q
Propagation Delay,
X
S
D
to
X
Q or
X
R
D
to Q
Propagation Delay,
X
S
D
to
X
Q or
X
R
D
to Q
Set- up Time,
X
J,
X
K to
X
CP
Hold Time,
X
J,
X
K to
X
CP
Removal Time,
X
S
D
,
X
R
D
to
X
CP
Pulse Width, CLK HIGH or LOW
Set or Reset Pulse Width, HIGH or LOW
Output Skew§
2.5
2
3
3.3
3
M in.
M a x.
9
11
10
V
CC
= 2.7V
M in.
M a x.
8.5
9
10
2.5
2
3
3.3
3
V
CC
= 3.3V ±0.3V
M in.
M a x.
7.5
8
9
2.5
2
3
3.3
3
500
ps
ns
Units
§
. Skew between any two outputs of the same package switching in the same direction.
Operating Characteristics, T
A
= 25°C
Parame te rs
Te s t
Conditions
f =10MHz
4
V
CC
= 1.8V
Typ.
V
CC
= 2.5V
Typ.
17
V
CC
= 3.3V
Typ.
20
PS8678
Units
C
p d
Power Dissipation Capacitance
15
pF
03/20/03
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PI74LVC109A
Fast CMOS 3.3V
Dual J-K Flip-Flop
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8V ±0.15V
2xVCC
1kΩ
From Output
Under Test
C
L
= 30pF
(See Note A)
S1
Open
GND
Te s t
1kΩ
S1
Open
2 x V
CC
GND
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
V
CC
Load Circuit
Asynchronous
Control
t
REM
Timing
Input
t
su
Data
Input
V
CC
V
CC
/2
0V
t
h
V
CC
V
CC
/2
V
CC
/2
0V
Input
0
t
W
V
CC
V
CC
/2
V
CC
/2
0V
Voltage Waveforms
Pulse Duration
Voltage Waveforms
Setup and Hold Times
V
CC
Input
V
CC
/2
t
PLH
V
CC
/2
t
PHL
Output
V
CC
/2
V
CC
/2
V
OL
t
PLH
V
CC
/2
0V
t
PHL
V
OH
Output
V
CC
/2
V
OL
V
OH
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
Output
Control
(Low Level
Enabling)
V
CC
V
CC
/2
t
PZL
V
CC
/2
t
PZH
V
CC
/2
V
CC
/2
0V
t
PLZ
V
CC
V
OL
+0.15V
t
PHZ
V
OH
–0.15V
V
OH
0V
V
OL
Voltage Waveforms
Propagation Delay Times
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, Z
O
= 50Ω, t
R
≤
2.0ns, t
F
≤
2.0ns.
D. Outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
F. t
PZL
and t
PZH
are the same as t
en
G. t
PLH
and t
PHL
are the same as t
pd
H. Not all parameters and waveforms are applicable to all devices.
5
PS8678
03/20/03
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