tion, signal buffering, voltage translation, cold- and warm-
sparing. The device can be used as two independant 8-bit
transceivers or one 16-bit transceiver. Data on the A or B bus
is clocked into the registers on the rising edge of the appropri-
ate clock (xCLKAB or xCLKBA) input. With either V
DD
sup-
ply equal to zero volts, the UT54ACS164646S outputs and
inputs present a minimum impedance of 750k making it
ideal for “cold-spare” and "warm-spare" applications. By vir-
tue of its flexible power supply interface, the
UT54ACS164646S may operate as a 3.3-volt only, 5-volt only,
or mixed 3.3V/5V bus transceiver.
The Output-enable (xOE) and direction-control (xDIR) inputs
are provided to control the tri-state function and input/output
direction of the transceiver respectively. The select controls
(xSAB and xSBA) select whether stored register data or real-
time data is driven to the outputs as determined by the xDIR
inputs. The circuitry used for select control eliminates the typ-
ical decoding glitch that occurs in a multiplexer during the
transition between stored and real-time data. Regardless of the
selected operating mode ("real-time" or "recall"), a rising edge
on the port input clocks (xCLKAB and xCLKBA) will latch
the corresponding I/O states into their respective registers.
Furthermore, when a data port is isolated (xOE = high), A-port
data may be stored into its corresponding register while B-port
data may be independantly stored into its corresponding regis-
ters. Therefore, when an output function is disabled, the input
function is still enabled and may be used to store and transmit
data. Lastly, only one of the two buses, xA-port or xB-port,
may be driven at a time.
PIN DESCRIPTION
Pin Names
xOE
xDIR
xAx
xBx
xSAB
xSBA
xCLKAB
xCLKBA
Description
Output Enable Input (Active Low)
Direction Control Inputs
Side A Inputs or 3-State Outputs (3.3V Port)
Side B Inputs or 3-State Outputs (5V Port)
Select real-time or stored A bus data to B bus
Select real-time or stored B bus data to A bus
Store A bus data
Store B bus data
1
56-Lead Flatpack
Pinout
1DIR
1CLKBA
1SBA
VSS
1B1
1B2
VDDB
1B3
1B4
1B5
VSS
1B6
1B7
1B8
2B1
2B2
2B3
VSS
2B4
2B5
2B6
VDDB
2B7
2B8
VSS
2SBA
2CLKBA
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1CLKAB
1SAB
VSS
1A1
1A2
VDDA
1A3
1A4
1A5
VSS
1A6
1A7
1A8
2A1
2A2
2A3
VSS
2A4
2A5
2A6
VDDA
2A7
2A8
VSS
2SAB
2CLKAB
2OE
LOGIC SYMBOL
56
1
1OE
1DIR
G3
3 EN1 (BA)
3 EN2 (AB)
C4
G5
C6
G7
G10
10 EN8 (BA)
10 EN9 (AB)
C11
G12
C13
G14
>1
1
6D
1
7
7
5
5 1
>1
2
51
49
1A2
4D
52
1A1
1CLKAB 55
54
1SAB
2
1CLKBA
3
1SBA
2OE 29
2DIR
2CLKAB
2SAB
2CLKBA
2SBA
28
30
31
27
26
1B1
5
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
6
8
9
10
12
13
14
15
8
13D
>1
14
1 14
12
12
11D
1
>1
9
1A3
48
1A4
47
1A5
45
1A6
44
1A7
43
1A8
42
2A1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
16
17
19
20
21
23
24
41
2A2
40
2A3
38
2A4
37
2A5
36
2A6
34
2A7
33
2A8
2
POWER TABLE
Port B
5 Volts
5 Volts
3.3 Volts
V
SS
V
SS
3.3V or 5V
Port A
3.3 Volts
5 Volts
3.3 Volts
V
SS
3.3V or 5V
V
SS
OPERATION
Voltage Translator
Non Translating
Non Translating
Cold Spare
Port A Warm Spare
Port B Warm Spare
I/O GUIDELINES
Control signals xDIR, xOE, xSAB, xSBA, xCLKAB, and
xCLKBA are powered by V
DDA
. All inputs are 5-volt tolerant.
When VDD2 is at 3.3 volts, either 3.3 or 5-volt CMOS logic
levels can be applied to all control inputs. Control signals
DIRx, /OEx, xSAB, xSBA, xCLKAB, and xCLKBA are pow-
ered by VDDA. All inputs are 5-volt tolerant. Additionally, it
is recommended that all unused inputs be tied to VSS through
a 1K to 10K resistor. It's good design practice to tie the un-
used input to VSS via a resistor to reduce noise susceptibility.
The resistor protects the input pin by limiting the current from
high going variations in VSS. The number of inputs that can be
tied to the resistor pull-down can vary. It is up to the system de-
signer to choose how many inputs are tied together by figuring
out the max load the part can drive while still meeting system
performance specs. Input signal transitions should be driven to
the device with a rise and fall time that is <100ms.
FUNCTION TABLE
Inputs
xOE
X
X
H
H
L
L
L
L
xDIR
X
X
X
X
L
L
H
H
xCLKAB
X
H or L
X
X
X
H or L
xCLKBA
X
H or L
X
H or L
X
X
xSAB
X
X
X
X
X
X
L
H
xSBA
X
X
X
X
L
H
X
X
POWER APPLICATION GUIDELINES
For proper operation connect power to all V
DDx
pins and
ground all V
SS
pins (i.e., no floating V
DDx
or V
SS
input pins).
By virtue of the UT54ACS164646S warm-spare feature, power
supplies V
DDB
and V
DDA
may be applied to the device in any
order. To ensure the device is in cold-spare mode, both sup-
plies, V
DDB
and V
DDA
, must be equal to V
SS
+/- 0.3V. Warm-
spare operation is in effect when one power supply is >1V and
the other power supply is equal to V
SS
+/- 0.3V. If V
DDB
has a
power-on ramp rate longer than 1 second, then V
DDA
should be
powered-on first to ensure proper control of xDIR and xOE.
During normal operation of the part, after power-up, ensure
V
DDB
> V
DDA
.
By definition, warm sparing occurs when half of the chip re-
ceives its normal VDD supply value while the VDD supplying
the other half of the chip is set to 0.0V. When the chip is ’warm
spared’, the side that has its VDD set to a normal operational
value is ’actively’ tristated because the chip’s internal OE sig-
nal is forced low. The side of the chip that has VDD set to 0.0V
is ’passively’ tristated by the cold spare circuitry.
In order to minimize transients and current consumption, the
user is encouraged to first apply a high level to the xOE pins
and then power down the appropriate supply.
Data I/O
+
xA1-xA8
Input
Unspecified
Input
Input
Output
Output
Input
Input
xB1-xB8
Unspecified
Input
Input
Input
Input
Input
Output
Output
Operation or Function
Store A, B unspecified
+
Store B, A unspecified
+
Store A and B data
+
Isolation, hold storage
Real-time B data to A bus
Recall stored B data to A bus
Real-time A data to B Bus
Recall stored A data to B bus
+
The data-output functions may be enabled or disabled by various signals xOE or xDIR. Data-input functions are always enabled, i.e. data at the bus terminals is
stored on every low-to-high transition of the clock inputs.
3
LOGIC DIAGRAM
OE1
56
DIR1 1
1CLKAB 55
1SAB 54
1CLKBA 2
1SBA 3
SEL
ENB
1B1 5
D Q
CLK
SEL
A
Y
B
1B2
1B3
1B4
1B5
1B6
1B7
1B8
6
8
9
10
12
13
14
Y
B
A
CLK
Q D
ENB
52 1A1
Seven Channels Identical
To Channel One Above
51
49
48
47
45
44
43
1A2
1A3
1A4
1A5
1A6
1A7
1A8
OE2
29
DIR2 28
2CLKAB 30
2SAB 31
2CLKBA 27
2SBA 26
SEL
ENB
2B1 15
D Q
CLK
SEL
A
Y
B
2B2
2B3
2B4
2B5
2B6
2B7
2B8
16
17
19
20
21
23
24
Y
B
A
CLK
Q D
ENB
42 2A1
Seven Channels Identical
To Channel One Above
41
40
38
37
36
34
33
2A2
2A3
2A4
2A5
2A6
2A7
2A8
4
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEL LET Threshold
SEU Onset LET Threshold
4
SEU Error Rate
2
Neutron Fluence
3
LIMIT
1.0E5
>110
>97 @4.5V, >74@ 3.0V
Immune @4.5V, 6.3E-10 @3.0V
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
errors/bit-day
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Adams 90% worst case particle environment, geosynchronous orbit, 100mils of Aluminum shielding
3. Not tested, inherent of CMOS technology.
4. Core logic is driven by
V
DDB.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/OB
(Port B)
2
V
I/OA
(Port A)
2
V
DDB
V
DDA
T
STG
T
J
JC
I
I
P
D
PARAMETER
Voltage any pin
Voltage any pin
Supply voltage
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT (Mil only)
-0.3 to 6.0
-0.3 to 6.0
-0.3 to 6.0
-0.3 to 6.0
-65 to +150
+175
20
10
250
UNITS
V
V
V
V
C
C
C/W
mA
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For cold spare mode (V
DDx
= V
SS
+/- 0.3V), V
I/Ox
may be -0.3V to the maximum recommended operating V
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