8S89832AKILF datasheet, PDF - EEWORLD Datasheet

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8S89832AKILF: DescriptionVFQFPN-16, Tube; Categorylogic logic; File Size598KB，15 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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VFQFPN-16, Tube

8S89832AKILF Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN
package instruction	3 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VEED-2/-4, VFQFN-16
Contacts	16
Manufacturer packaging code	NLG16P2
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	VFQFN- N 3 X 3 X 1.0 MM - NO LEAD
series	89832
Input adjustment	DIFFERENTIAL
JESD-30 code	S-XQCC-N16
JESD-609 code	e3
length	3 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC16,.12SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Prop。Delay @ Nom-Sup	0.55 ns
propagation delay (tpd)	0.55 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.025 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	3 mm

8S89832AKILF Preview

Low Skew, 1-to-4 Differential-to-LVDS

Fanout Buffer

8S89832I

Data Sheet

Description

The 8S89832I is a high speed 1-to-4 Differential-to-LVDS Fanout

Buffer. The 8S89832I is optimized for high speed and very low output

skew, making it suitable for use in demanding applications such as

SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The

internally terminated differential input and V

REF

pin allow other

differential signal families such as LVPECL, LVDS, and SSTL to be

easily interfaced to the input with minimal use of external

components. The device also has an output enable pin that may be

useful for system test and debug purposes.

The 8S89832I is packaged in a small 3mm x 3mm 16-pin VFQFN

package which makes it ideal for use in space-constrained

applications.

Features

•

Four differential LVDS output pairs

IN, nIN input pairs can accept the following differential input levels:

LVPECL, LVDS, SSTL

50 internal input termination to V

Maximum output frequency: 2GHz

Output skew: 25ps (maximum)

Part-to-part skew: 200ps (maximum)

Propagation delay: 550ps (maximum)

Additive phase jitter, RMS: 0.09ps (typical)

Full 2.5V supply mode

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) package

Block Diagram

nQ0

nIN

REF_AC

CLK

nQ3

nQ2

50Ω

Pin Assignment

GND

nQ0

Q1 1

nQ1

16 15 14 13

12 IN

11 V

10 V

REF_AC

9 nIN

nQ1

50Ω

Q2 3

nQ2 4

nQ3

8S89832I

16-Lead VFQFN

3mm x 3mm x 0.925mm package body

K Package

Top View

September 22, 2017

8S89832I Data Sheet

Table 1. Pin Descriptions

Number

1, 2

3, 4

5, 6

7, 14

Name

Q1, nQ1

Q2, nQ2

Q3, nQ3

Output

Power

Type

Description

Differential output pair. LVDS interface levels.

Positive supply pins.

Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will

go HIGH on the next LOW transition at IN inputs. Input threshold is V

/2V. Includes a

37k



pullup resistor. Default state is HIGH when left floating. The internal latch is

clocked on the falling edge of the input signal IN. See Table 3A

LVTTL / LVCMOS interface levels.

Inverting differential clock input. 50



internal input termination to V

Reference voltage for AC-coupled applications.

Termination input.

Non-inverting differential clock input. 50



internal input termination to V

Power supply ground.

Differential output pair. LVDS interface levels.

Input

Pullup

15, 16

nIN

REF_AC

GND

Q0, nQ0

Input

Output

Input

Power

Output

NOTE:

Pullup

refers to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

PULLUP

Parameter

Input Capacitance

Input Pullup Resistor

Test Conditions

Minimum

Typical

Maximum

Units



September 22, 2017

8S89832I Data Sheet

Function Tables

Table 3A. Control Input Function Table

Input

Q[0:3]

Disabled; LOW

Enabled

Outputs

nQ[0:3]

Disabled; HIGH

Enabled

NOTE: EN switches, the clock outputs are disabled or enabled

following a falling input clock edge as shown in

Figure 1.

Figure 1. EN Timing Diagram

nIN

nQx

→

←

Table 3B. Truth Table

Inputs

nIN

Outputs

Q[0:3]

(NOTE 1)

nQ[0:3]

(NOTE 1)

NOTE 1: On next negative transition of the input signal (IN).

September 22, 2017

8S89832I Data Sheet

Absolute Maximum Ratings

Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the

DC Characteristics or AC Characteristics

is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Supply Voltage, V

Inputs, V

Outputs, I

Continuous Current

Surge Current

Input Current, IN, nIN

Current, I

Input Sink/Source, I

REF_AC

Operating Temperature Range, T

Package Thermal Impedance,



, (Junction-to-Ambient)

Storage Temperature, T

STG

Rating

4.6V

-0.5V to V

+ 0.5V

10mA

15mA

±50mA

±100mA

± 0.5mA

-40°C to +85°C

74.7C/W (0 mps)

-65C to 150C

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Symbol

Parameter

Positive Supply Voltage

Power Supply Current

Test Conditions

Minimum

2.375

Typical

2.5

Maximum

2.625

Units

Table 4B. LVCMOS/LVTTL DC Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Symbol

Parameter

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

= V

= 2.625V

= 2.625V, V

= 0V

-150

Test Conditions

Minimum

1.7

-0.3

Typical

Maximum

+ 0.3

0.7

Units

µA

September 22, 2017

8S89832I Data Sheet

Table 4C. Differential DC Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Symbol

DIFF_IN

REF_AC

Parameter

Differential Input Resistance

Input High Voltage

Input Low Voltage

Input Voltage Swing; NOTE 1

Differential Input Voltage Swing

Input Current; NOTE 2

Reference Voltage

IN, nIN

– 1.40

– 1.35

IN, nIN

Test Conditions

IN to VT, nIN to VT

Minimum

1.2

0.15

0.3

– 1.30

Typical

Maximum

– 0.15

1.2

Units



NOTE 1: V

should not be less than -0.3V.

NOTE 2: Guaranteed by design.

Table 4D. LVDS DC Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Symbol

V

Parameter

Differential Output Voltage

Magnitude Change

Offset Voltage

Magnitude Change

1.125

Test Conditions

Minimum

247

Typical

Maximum

454

1.375

Units

AC Electrical Characteristics

Table 5. AC Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Symbol

OUT

tsk(o)

tsk(pp)

tjit

/ t

Parameter

Operating Frequency

Propagation Delay; (Differential)

NOTE 1

Output Skew; NOTE 2, 3

Part-to-Part Skew; NOTE 3, 4

Buffer Additive Phase Jitter, RMS; refer to

Additive Phase Jitter Section

Clock Enable Setup Time

Output Rise/Fall Time

EN to IN, nIN

20% to 80%

200MHz, Integration Range:

12kHz - 20MHz

300

235

0.09

300

Test Conditions

Minimum

Typical

Maximum

550

200

Units

GHz

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

All parameters are measured at



1.5GHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

September 22, 2017

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8S89832AKILF Related Products

	8S89832AKILF	8S89832AKILFT
Description	VFQFPN-16, Tube	VFQFPN-16, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN	VFQFPN
package instruction	3 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VEED-2/-4, VFQFN-16	3 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VEED-2/-4, VFQFN-16
Contacts	16	16
Manufacturer packaging code	NLG16P2	NLG16P2
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Samacsys Description	VFQFN- N 3 X 3 X 1.0 MM - NO LEAD	VFQFN- N 3 X 3 X 1.0 MM - NO LEAD
series	89832	S
Input adjustment	DIFFERENTIAL	STANDARD
JESD-30 code	S-XQCC-N16	S-XQCC-N16
JESD-609 code	e3	e3
length	3 mm	3 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	16	16
Actual output times	4	4
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Encapsulate equivalent code	LCC16,.12SQ,20	LCC16,.12SQ,20
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260	260
power supply	2.5 V	2.5 V
Prop。Delay @ Nom-Sup	0.55 ns	0.55 ns
propagation delay (tpd)	0.55 ns	0.55 ns
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.025 ns	0.025 ns
Maximum seat height	1 mm	1 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	3 mm	3 mm

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