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Datasheet> All Categories > storage> storage> WME128K8-150CMA
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WME128K8-150CMA

Description
EEPROM, 128KX8, 150ns, Parallel, CMOS, CDIP32, 0.600 INCH, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32
Categorystorage    storage   
File Size820KB，12 Pages
ManufacturerMercury Systems Inc
Download Datasheet Parametric View All

WME128K8-150CMA Overview

EEPROM, 128KX8, 150ns, Parallel, CMOS, CDIP32, 0.600 INCH, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32

WME128K8-150CMA Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMercury Systems Inc
package instructionDIP,
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time150 ns
Other featuresWRITE ENDURANCE 10000 CYCLES; 10 YEARS DATA RETENTION; HARDWARE AND SOFTWARE DATA PROTECTION
Data retention time - minimum10
Durability10000 Write/Erase Cycles
JESD-30 codeR-CDIP-T32
JESD-609 codee0
length42.4 mm
memory density1048576 bit
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height5.13 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width15.24 mm
Maximum write cycle time (tWC)10 ms

WME128K8-150CMA Preview

WME128K8-XXX
128Kx8 CMOS MONOLITHIC EEPROM, SMD 5962-96796
FEATURES

Read Access Times of 125, 140, 150, 200, 250, 300ns

JEDEC Approved Packages
• 32 pin, Hermetic Ceramic, 0.600" DIP
(Package 300)
• 32 lead, Hermetic Ceramic, 0.400" SOJ
(Package 101)

Commercial, Industrial and Military Temperature Ranges

MIL-STD-883 Compliant Devices Available

Write Endurance 10,000 Cycles

Data Retention at 25°C, 10 Years

Low Power CMOS Operation

Automatic Page Write Operation
• Internal Address and Data Latches for 128 Bytes
• Internal Control Timer

Page Write Cycle Time 10ms Max.

Data Polling for End of Write Detection

Hardware and Software Data Protection

TTL Compatible Inputs and Outputs
This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
A0-16
I/O0-7
CS#
OE#
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
PIN DESCRIPTION
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0v Power
Ground
32 DIP
32 CSOJ
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 8
© 2014 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WME128K8-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE# and A9
Symbol
T
A
T
STG
V
G
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
Unit
°C
°C
V
V
CS#
H
L
L
X
X
X
OE#
X
L
H
H
X
L
TRUTH TABLE
WE#
X
H
L
X
H
X
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAPACITANCE
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
Symbol
V
CC
V
IH
V
IL
T
A
T
A
Min
4.5
2.0
-0.5
-55
-40
Max
5.5
V
CC
+ 0.3
+0.8
+125
+85
Unit
V
V
V
°C
°C
Parameter
Input Capacitance
Output Capacitance
T
A
= +25°C
Symbol
C
IN
C
OUT
Conditions
V
IN
= 0 V, f = 1MHz
V
I/O
= 0 V, f = 1MHz
Max
20
20
Unit
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
Symbol
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 2.1mA, V
CC
= 4.5V
I
OH
= -400μA, V
CC
= 4.5V
Min
Max
10
10
80
0.625
0.45
2.4
Unit
μA
μA
mA
mA
V
V
FIGURE 2 – AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
IOL
Current Source
D.U.T
Ceff = 50 pf
Vz ~ 1.5V
~
Bipolar Supply
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Current Source
IOH
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 8
© 2014 Microsemi Corporation. All rights reserved.
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WME128K8-XXX
READ
Figure 3 shows Read cycle waveforms. A read cycle begins with
selection address, chip select and output enable. Chip select is
accomplished by placing the CS# line low. Output enable is done
by placing the OE# line low. The memory places the selected data
byte on I/O0 through I/O7 after the access time. The output of the
memory is placed in a high impedance state shortly after either
the OE# line or CS# line is returned to a high level.
FIGURE 3 – READ WAVEFORMS
t
RC
ADDRESS
ADDRESS VALID
CS#
t
ACS
OE#
t
ACC
OUTPUT
NOTE:
OE# may be delayed up to t
ACS
- t
OE
after the falling edge of CS#
without impact on t
OE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
t
OE
t
DF
t
OH
OUTPUT
VALID
HIGH Z
AC READ CHARACTERISTICS
(See Figure 3)
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Read Cycle Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE#
or CS#
Output Enable to Output Valid
Chip Select or OE# to High Z Output
Symbol
t
RC
t
ACC
t
ACS
t
OH
t
OE
t
DF
-125
Min
125
Max
125
125
0
55
63
0
55
70
Min
140
-140
Max
140
140
0
55
70
Min
150
-150
Max
150
150
0
55
70
Min
200
-200
Max
200
200
0
85
70
Min
250
-250
Max
250
250
0
85
70
Min
300
-300
Max
300
300
Unit
ns
ns
ns
ns
ns
ns
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 8
© 2014 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WME128K8-XXX
WRITE
Write operations are initiated when both CS# and WE# are low
and OE# is high. The EEPROM devices support both a CS# and
WE# controlled write cycle. The address is latched by the falling
edge of either CS# or WE#, whichever occurs last.
The data is latched internally by the rising edge of either CS#
or WE#, whichever occurs first. A byte write operation will
automatically continue to completion.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships. A write
cycle begins with address application, write enable and chip select.
Chip select is accomplished by placing the CS# line low. Write
enable consists of setting the WE# line low. The write cycle begins
when the last of either CS# or WE# goes low.
The WE# line transition from high to low also initiates an internal
150μsec delay timer to permit page mode operation. Each
subsequent WE# transition from high to low that occurs before the
completion of the 150μsec time out will restart the timer from zero.
The operation of the timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
Data Hold Time
Chip Select Hold Time
Data Set-up Time
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
Symbol
t
WC
t
AS
t
WP
t
CS
t
AH
t
DH
t
CH
t
DS
t
OES
t
OEH
t
WPH
10
100
0
100
10
0
50
0
0
50
128Kx8
Min
Max
10
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 8
© 2014 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WME128K8-XXX
FIGURE 4 – WRITE WAVEFORMS WE# CONTROLLED
t
WC
OE#
t
OES
ADDRESS
t
AS
CS#
t
CS
WE
#
t
WP
t
DS
DATA IN
t
WPH
t
DH
t
AH
t
CSH
t
OEH
FIGURE 5 – WRITE WAVEFORMS CS# CONTROLLED
t
WC
OE#
t
OES
ADDRESS
t
AS
WE
#
t
CS
CS
#
t
WP
t
DS
DATA IN
t
WPH
t
DH
t
AH
t
CSH
t
OEH
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 8
© 2014 Microsemi Corporation. All rights reserved.
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
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