8701CY datasheet, PDF - EEWORLD Datasheet

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8701CY: DescriptionLow Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48; Categorylogic logic; File Size163KB，13 Pages; ManufacturerIDT (Integrated Device Technology)

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8701CY Overview

Low Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48

8701CY Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
Contacts	48
Reach Compliance Code	not_compliant
ECCN code	EAR99
series	8701
Input adjustment	STANDARD
JESD-30 code	S-PQFP-G48
JESD-609 code	e0
length	7 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
MaximumI(ol)	0.036 A
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	48
Actual output times	20
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP48,.35SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	2.5/3.3,3.3 V
Prop。Delay @ Nom-Sup	3.6 ns
propagation delay (tpd)	3.6 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	7 mm
minfmax	250 MHz

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KEW

÷1, ÷2

LVCMOS/LVTTL C

LOCK

ENERATOR

ENERAL

ESCRIPTION

The ICS8701 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Clock

Generator . The low impedance LVCMOS outputs are

designed to drive 50Ω series orparallel terminated

transmission lines. The effective fanout can be increased

from 20 to 40 by utilizing the ability of the outputs to drive

two series terminated lines.

The divide select inputs, DIV_SELx, control the output

frequency of each bank. The outputs can be utilized in the

÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank

enable inputs, BANK_EN0:1, support enabling and

disabling each bank of outputs individually. The master

reset input, nMR/OE, resets the internal frequency dividers

and also controls the active and high impedance states of

all outputs.

The ICS8701 is characterized at 3.3V and mixed

3.3V input supply, and 2.5V output supply operating

modes. Guaranteed bank, output and part-to-part skew

characteristics make the ICS8701 ideal for those clock

distribution applications demanding well defined

performance and repeatability.

ICS8701

EATURES

• Twenty LVCMOS outputs, 7Ω typical output impedance

• One LVCMOS/LVTTL clock input

• Maximum output frequency: 250MHz

• Bank enable logic allows unused banks to be disabled

in reduced fanout applications

• Output skew: 250ps (maximum)

• Part-to-part skew: 600ps (maximum)

• Bank skew: 200ps (maximum)

• Multiple frequency skew: 300ps (maximum)

• 3.3V or mixed 3.3V input, 2.5V output operating

supply modes

• 0°C to 70°C ambient operating temperature

• Other divide values available on request

• Available in both standard and lead-free RoHS compliant

packages

LOCK

IAGRAM

CLK

÷1

÷2

DIV_SELA

QB0:QB4

DIV_SELB

QC0:QC4

DIV_SELC

QD0:QD4

DIV_SELD

nMR/OE

BANK_EN0

BANK_EN1

Bank Enable

Logic

QA0:QA4

SSIGNMENT

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

GND

QB2

GND

QB3

DDO

QB4

QC0

DDO

QC1

GND

QC2

GND

QC3

DDO

QC4

QD0

DDO

QD1

GND

QD2

GND

QD3

DDO

QD4

ICS8701

QB1

DDO

QB0

QA4

DDO

QA3

GND

QA2

GND

QA1

DDO

QA0

DIV_SELA

DIV_SELB

CLK

GND

BANK_EN0

GND

BANK_EN1

nMR/OE

DIV_SELC

DIV_SELD

48-Pin LQFP

7mm x 7mm x 1.4mm

Y Package

Top View

8701CY

www.idt.com

REV. E JULY 31, 2010

8701CY Related Products

	8701CY
Description	Low Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
Contacts	48
Reach Compliance Code	not_compliant
ECCN code	EAR99
series	8701
Input adjustment	STANDARD
JESD-30 code	S-PQFP-G48
JESD-609 code	e0
length	7 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
MaximumI(ol)	0.036 A
Humidity sensitivity level	3
Number of functions	1
Number of terminals	48
Actual output times	20
Maximum operating temperature	70 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP48,.35SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	2.5/3.3,3.3 V
Prop。Delay @ Nom-Sup	3.6 ns
propagation delay (tpd)	3.6 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	7 mm
minfmax	250 MHz

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