8701CYI datasheet, PDF - EEWORLD Datasheet

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8701CYI: DescriptionLow Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48; Categorylogic logic; File Size224KB，14 Pages; ManufacturerIDT (Integrated Device Technology)

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8701CYI Overview

Low Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48

8701CYI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48
Contacts	48
Reach Compliance Code	not_compliant
ECCN code	EAR99
series	8701
Input adjustment	STANDARD
JESD-30 code	S-PQFP-G48
JESD-609 code	e0
length	7 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	48
Actual output times	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
propagation delay (tpd)	3.7 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	7 mm

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KEW

÷1, ÷2

LOCK

ENERATOR

ENERAL

ESCRIPTION

The ICS8701I is a low skew, ÷1, ÷2 Clock Generator. The

low impedance LVCMOS outputs are designed to drive 50Ω

series or parallel terminated transmission lines. The

effective fanout can be increased from 20 to 40 by utilizing

the ability of the outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx, control the output

frequency of each bank. The outputs can be utilized in the ÷1,

÷2 or a combination of ÷1 and ÷2 modes. The bank enable

inputs, BANK_EN0:1, support enabling and disabling each

bank of outputs individually. The master reset input, nMR/OE,

resets the internal frequency dividers and also controls the

active and high impedance states of all outputs.

The ICS8701I is characterized at 3.3V and mixed 3.3V input

supply, and 2.5V output supply operating modes. Guaranteed

bank, output and part-to-part skew characteristics make the

ICS8701I ideal for those clock distribution applications de-

manding well defined performance and repeatability.

ICS8701I

EATURES

• Twenty LVCMOS outputs, 7Ω typical output impedance

• LVCMOS / LVTTL clock input

• Maximum input frequency: 250MHz

• Bank enable logic allows unused banks to be disabled

in reduced fanout applications

• Bank skew: 200ps

• Output skew: 250ps

• Multiple frequency skew: 300ps

• Part-to-part skew: 600ps

• 3.3V or mixed 3.3V input, 2.5V output operating supply

• -40°C to 85°C ambient operating temperature

• Other divide values available on request

• Available in both standard and lead-free RoHS compliant

packages

LOCK

IAGRAM

CLK

÷1

÷2

DIV_SELA

QB0:QB4

DIV_SELB

QC0:QC4

DIV_SELC

QD0:QD4

DIV_SELD

nMR/OE

BANK_EN0

BANK_EN1

Bank Enable

Logic

QA0:QA4

SSIGNMENT

GND

QB2

GND

QB3

DDO

QB4

QC0

DDO

QC1

GND

QC2

GND

QC3

DDO

QC4

QD0

DDO

QD1

GND

QD2

GND

QD3

DDO

QD4

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

ICS8701I

QB1

DDO

QB0

QA4

DDO

QA3

GND

QA2

GND

QA1

DDO

QA0

48-Pin LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

DIV_SELA

DIV_SELB

CLK

GND

DDI

BANK_EN0

GND

BANK_EN1

DDI

nMR/OE

DIV_SELC

DIV_SELD

8701CYI

www.idt.com

REV. C JULY 27, 2010

8701CYI Related Products

	8701CYI	8701CYIT
Description	Low Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48	Low Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP
package instruction	7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48	7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48
Contacts	48	48
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
series	8701	8701
Input adjustment	STANDARD	STANDARD
JESD-30 code	S-PQFP-G48	S-PQFP-G48
JESD-609 code	e0	e0
length	7 mm	7 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	48	48
Actual output times	20	20
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
propagation delay (tpd)	3.7 ns	3.7 ns
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns	0.25 ns
Maximum seat height	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
width	7 mm	7 mm

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