8745BYLF datasheet, PDF - EEWORLD Datasheet

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8745BYLF: DescriptionClock Driver, 8745 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC-HD, LQFP-32; Categorylogic logic; File Size726KB，20 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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8745BYLF Overview

Clock Driver, 8745 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC-HD, LQFP-32

8745BYLF Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC-HD, LQFP-32
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
series	8745
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-PQFP-G32
JESD-609 code	e3
length	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	5
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	3.7 ns
propagation delay (tpd)	4 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.035 ns
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm
minfmax	31.25 MHz

8745BYLF Preview

1:5 Differential-to-LVDS Zero Delay

Clock Generator

ICS8745B

DATA SHEET

General Description

The ICS8745B is a highly versatile 1:5 LVDS Clock

Generator and a member of the HiPerClockS™ family

HiPerClockS™

of High Performance Clock Solutions from IDT. The

ICS8745B has a fully integrated PLL and can be

configured as zero delay buffer, multiplier or divider,

and has an output frequency range of 31.25MHz to 700MHz. The

Reference Divider, Feedback Divider and Output Divider are each

programmable, thereby allowing for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external

feedback allows the device to achieve “zero delay” between the input

clock and the output clocks. The PLL_SEL pin can be used to

bypass the PLL for system test and debug purposes. In bypass

mode, the reference clock is routed around the PLL and into the

internal output dividers.

Features

•

Five differential LVDS outputs designed to meet

or exceed the requirements of ANSI TIA/EIA-644

Selectable differential clock inputs

CLKx, nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

Output frequency range: 31.25MHz to 700MHz

Input frequency range: 31.25MHz to 700MHz

VCO range: 250MHz to 700MHz

External feedback for “zero delay” clock regeneration

with configurable frequencies

Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

Cycle-to-cycle jitter: 30ps (maximum)

Output skew: 35ps (maximum)

Static phase offset: 25ps ± 125ps

Full 3.3V supply voltage

0°C to 70°C ambient operating temperature

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

ICS

Block Diagram

nQ0

PLL_SEL

Pullup

Pin Assignment

PLL_SEL

SEL3

DDA

CLK0

Pulldown

nCLK0

Pullup

CLK1

Pulldown

nCLK1

Pullup

CLK_SEL

Pulldown

FB_IN

Pulldown

nFB_IN

Pullup

÷1, ÷2, ÷4, ÷8,

÷16, ÷32

÷64

nQ1

nQ2

nQ3

nQ4

SEL0

SEL1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

32 31 30 29 28 27 26 25

GND

DDO

nQ4

nQ3

DDO

nQ2

GND

nQ1

PLL

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

10 11 12 13 14 15 16

nFB_IN

FB_IN

SEL2

GND

DDO

nQ0

SEL0

Pulldown

SEL1

Pulldown

SEL2

Pulldown

SEL3

Pulldown

ICS8745B

32-Lead LQFP 7mm x 7mm x 1.4mm

package body

Top View

ICS8745BY REVISION D JUNE 29, 2009

ICS8745B Data Sheet

1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Table 1. Pin Descriptions

Number

1, 2,

12, 29

Name

SEL0, SEL1,

SEL2 SEL3

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

Input

Type

Pulldown

Pullup

Pulldown

Pullup

Pulldown

Description

Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.

Non-inverting differential clock input.

Inverting differential clock input.

Non-inverting differential clock input.

Inverting differential clock input.

Clock select input. When HIGH, selects CLK1,nCLK1. When LOW, selects CLK0,

nCLK0. LVCMOS / LVTTL interface levels.

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Qx to go low and the inverted outputs nQx to go high.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS / LVTTL interface levels.

Core supply pins.

Pullup

Pulldown

Inverting differential feedback input to phase detector for regenerating clocks with

“Zero Delay.”

Non-inverted differential feedback input to phase detector for regenerating clocks

with “Zero Delay.”

Power supply ground.

Differential output pair. LVDS interface levels.

Output supply pins.

Differential output pair. LVDS interface levels.

Analog supply pin.

Pullup

PLL select. Selects between the PLL and reference clock as the input to the

dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels.

Input

Pulldown

9, 32

13, 19, 25

14, 15

16, 22, 28

17, 18

20, 21

23, 24

26, 27

FBIN

GND

nQ0/Q0

DDO

nQ1/Q1

nQ2/Q2

nQ3/Q3

nQ4/Q4

DDA

PLL_SEL

Power

Input

Power

Output

Power

Output

Power

Input

NOTE:

Pullup and Pulldown

refer to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

PULLUP

PULLDOWN

Parameter

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Test Conditions

Minimum

Typical

Maximum

Units

Ω

ICS8745BY REVISION D JUNE 29, 2009

ICS8745B Data Sheet

1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Function Tables

Table 3A. Control Input Function Table

Inputs

Outputs

PLL_SEL = 1

PLL Enable Mode

Reference Frequency Range (MHz)*

250 - 700

125 - 350

62.5 - 175

31.25 - 87.5

250 - 700

125 - 350

62.5 - 175

250 - 700

125 - 350

250 - 700

125 - 350

62.5 - 175

31.25 - 87.5

62.5 - 175

31.25 - 87.5

Q[0:4], nQ[0:4]

÷1

÷2

÷4

÷8

SEL3

SEL2

SEL1

SEL0

*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.

ICS8745BY REVISION D JUNE 29, 2009

ICS8745B Data Sheet

1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Table 3B. PLL Bypass Function Table

Inputs

Outputs

PLL_SEL = 0

PLL Bypass Mode

SEL1

SEL0

Q[0:4], nQ[0:4]

÷4

÷8

÷16

÷32

÷64

÷2

÷4

÷1

÷2

÷1

SEL3

SEL2

ICS8745BY REVISION D JUNE 29, 2009

ICS8745B Data Sheet

1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the

DC Characteristics or AC Characteristics

is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Supply Voltage, V

Inputs, V

Outputs, I

Continuos Current

Surge Current

Package Thermal Impedance,

Storage Temperature, T

STG

Rating

4.6V

-0.5V to V

+ 0.5V

10mA

15mA

47.9°C/W (0 lfpm)

-65°C to 150°C

DC Electrical Characteristics

Table 4A. LVDS Power Supply DC Characteristics,

= V

DDO

= 3.3V ± 5%, T

= -0°C to 70°C

Symbol

DDA

DDO

DDA

DDO

Parameter

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

Output Supply Current

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

125

Units

Table 4B. LVCMOS/LVTTL DC Characteristics,

= V

DDO

= 3.3V ± 5%, T

= 0°C to 70°C

Symbol

Parameter

Input High Voltage

Input Low Voltage

CLK_SEL,

SEL[0:3], MR

PLL_SEL

CLK_SEL,

SEL[0:3], MR

PLL_SEL

= V

= 3.465V

= V

= 3.465V

= 3.465V, V

= 0V

= 3.465V, V

= 0V

-5

-150

Test Conditions

Minimum

-0.3

Typical

Maximum

+ 0.3

0.8

150

Units

µA

Input High Current

Input Low Current

ICS8745BY REVISION D JUNE 29, 2009

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

8745BYLF Related Products

	8745BYLF	8745BYLFT
Description	Clock Driver, 8745 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC-HD, LQFP-32	PLL Based Clock Driver, 8745 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC-HD, LQFP-32
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP
package instruction	7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC-HD, LQFP-32	7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC-HD, LQFP-32
Contacts	32	32
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
series	8745	8745
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-PQFP-G32	S-PQFP-G32
JESD-609 code	e3	e3
length	7 mm	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	32	32
Actual output times	5	5
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32	QFP32,.35SQ,32
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	3.7 ns	3.7 ns
propagation delay (tpd)	4 ns	4 ns
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.035 ns	0.035 ns
Maximum seat height	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	7 mm	7 mm
minfmax	31.25 MHz	31.25 MHz

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