512Kx8 CMOS EEPROM
SMD 5962-93091
WE512K / 256K / 128K8-XCX
512Kx8 BIT CMOS EEPROM MODULE
FEATURES
Read Access Times of 150, 200, 250, 300ns
JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package
300)
Commercial, Industrial and Military Temperature Ranges
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
• 3mA Standby Typical/100mA Operating Maximum
Automatic Page Write Operation
• Internal Address and Data Latches for
• 512 Bytes, 1 to 128 Bytes/Row, Four Pages
Page Write Cycle Time 10mS Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
FIGURE 1 – PIN CONFIGURATION
TOP VIEW
A0-18
I/O0-7
CS#
OE#
WE#
V
CC
V
SS
PIN DESCRIPTION
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
BLOCK DIAGRAM
A
0-16
I/O
0-7
WE#
OE#
128K x 8
128K x 8
128K x 8
128K x 8
A
17
A
18
CS#
Decoder
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
1
4312.08E-0718-ss-WE512K_256K_128K8-XCX
WE512K / 256K / 128K8-XCX
256Kx8 BIT CMOS EEPROM Module
FEATURES
Read Access Times of 150, 200ns
JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package
302)
Commercial, Industrial and Military Temperature Ranges
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
• 2mA Standby Typical/90mA Operating Maximum
Automatic Page Write Operation
• Internal Address and Data Latches for
• 512 Bytes, 1 to 64 Bytes/Row, Eight Pages
Page Write Cycle Time 10mS Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
FIGURE 2 – PIN CONFIGURATION
TOP VIEW
A0-18
I/O0-7
CS#
OE#
WE#
V
CC
V
SS
PIN DESCRIPTION
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
BLOCK DIAGRAM
A
0-14
I/O
0-7
WE#
OE#
1
32K x 8
2
32K x 8
8
32K x 8
A
15
A
16
A
17
CS#
Decoder
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
2
4312.08E-0718-ss-WE512K_256K_128K8-XCX
WE512K / 256K / 128K8-XCX
128Kx8 BIT CMOS EEPROM Module
FEATURES
Read Access Times of 150, 200ns
JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package
300)
Commercial, Industrial and Military Temperature Ranges
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
• 1mA Standby Typical/70mA Operating
Automatic Page Write Operation
• Internal Address and Data Latches for
• 256 Bytes, 1 to 64 Bytes/Row, Four Pages
Page Write Cycle Time 10mS Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
FIGURE 3 – PIN CONFIGURATION
TOP VIEW
A0-18
I/O0-7
CS#
OE#
WE#
V
CC
V
SS
PIN DESCRIPTION
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
BLOCK DIAGRAM
A
0-14
I/O
0-7
WE#
OE#
32K x 8
32K x 8
32K x 8
32K x 8
A
15
A
16
CS#
Decoder
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
3
4312.08E-0718-ss-WE512K_256K_128K8-XCX
WE512K / 256K / 128K8-XCX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Any Pin
Voltage on OE# and A9
Thermal Resistance junction to case
Lead Temperature (soldering -10 secs)
Symbol
T
A
T
STG
V
G
JC
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
28
+300
Unit
°C
°C
V
V
°C/W
°C
CS#
H
L
L
X
X
X
OE#
X
L
H
H
X
L
WE#
X
H
L
X
H
X
TRUTH TABLE
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAPACITANCE
T
A
= +25°C
Parameter
Input Capacitance
Output Capacitance
Sym
C
IN
C
OUT
Condition
V
IN
= 0V, f = 1MHz
V
I/O
= 0V, f = 1MHz
512Kx8 256Kx8 128Kx8
Unit
Max
Max
Max
45
60
80
80
45
60
pF
pF
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
Symbol
V
CC
V
IH
V
IL
T
A
T
A
Min
4.5
2.0
-0.3
-55
-40
Max
5.5
V
CC
+ 0.3
+0.8
+125
+85
Unit
V
V
V
°C
°C
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Dynamic Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, Vout = GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 2.1mA, V
CC
= 4.5V
I
OH
= -400μA, V
CC
= 4.5V
Min
512K x 8
Typ
Max
10
10
80
100
3
8
0.45
Min
256K x 8
Typ
Max
10
10
60
90
2
6
0.45
Min
128K x 8
Typ
Max
10
10
50
90
1
4
0.45
Unit
μA
μA
mA
mA
V
V
2.4
2.4
2.4
NOTE: DC test conditions: Vih = Vcc -0.3V, Vil = 0.3V
FIGURE 4 – AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
Notes: V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
4
4312.08E-0718-ss-WE512K_256K_128K8-XCX
WE512K / 256K / 128K8-XCX
READ
Figure 5 shows Read cycle waveforms. A read cycle begins with
selection address, chip select and output enable. Chip select is
accomplished by placing the CS# line low. Output enable is done
by placing the OE# line low. The memory places the selected data
byte on I/O0 through I/O7 after the access time. The output of the
memory is placed in a high impedance state shortly after either the
OE# line or CS# line is returned to a high level.
FIGURE 5 – READ WAVEFORMS
ADDRESS
CS#
OE#
OUTPUT
NOTE:
OE# may be delayed up to t
ACS
-t
OE
after the falling edge of CS# without
impact on t
OE
or by t
ACC
-t
OE
after an
address change without impact on t
ACC
.
AC READ CHARACTERISTICS
(See Figure 5)
FOR WE512K8-XCX
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or Output Enable to High Z Output
Symbol
trc
tacc
tacs
toh
toe
tdf
-150
Min
150
Max
150
150
0
85
70
0
85
70
Min
200
-200
Max
200
200
0
100
70
Min
250
-250
Max
250
250
0
125
70
Min
300
-300
Max
300
300
Unit
ns
ns
ns
ns
ns
ns
FOR WE256K8-XCX and WE128K8-XCX
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or Output Enable to High Z Output
Symbol
trc
tacc
tacs
toh
toe
tdf
-150
Min
150
Max
150
150
0
85
70
0
85
70
Min
200
-200
Max
200
200
Unit
ns
ns
ns
ns
ns
ns
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
5
4312.08E-0718-ss-WE512K_256K_128K8-XCX
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