CMOS DUAL SyncFIFO™
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1024 x 18
Integrated Device Technology, Inc.
IDT72805LB
IDT72815LB
IDT72825LB
FEATURES:
• The 72805 is equivalent to two 72205LB 256 x 18
FIFOs
• The 72815 is equivalent to two 72215LB 512 x 18
FIFOs
• The 72825 is equivalent to two 72225LB 1024 x 18
FIFOs
• Offers optimal combination of large capacity (2K), high
speed, design flexibility, and small footprint
• Ideal for the following applications:
- Network switching
- Two level prioritization of parallel data
- Bidirectional data transfer
- Busmatching between 18-bit and 36-bit data paths
- Width expansion to 36-bit per package
- Depth expansion to 2048 words per package
• 20ns read/write cycle time, 12ns access time
• Read and write clocks can be asynchronous or coinci-
dent (permits simultaneous reading and writing of data
on a single clock edge)
• Programmable almost-empty and almost-full flags
• Empty and Full flags signal FIFO status
• Half-Full flag capability in single device configuration
• Enable puts output data bus in high impedance state
• High-performance submicron CMOS technology
• Available in a 121-lead, 16 x 16 mm plastic Ball Grid
Array (BGA)
• Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72805LB/72815LB/72825LB are dual 18-bit-wide
synchronous (clocked) first-in, first-out (FIFO) memories.
These devices are functionally equivalent to two IDT72205LB/
72215LB/72225LB FIFOs in a single package with all associ-
ated control, data, and flag lines assigned to independent
pins. These FIFOs are applicable for a wide variety of data
buffering needs, such as optical disk controllers, local area
networks (LANs), and interprocessor communication.
Each of the two FIFOs contained in the IDT72805LB/
72815LB/72825LB has an 18-bit input data port (D0 - D17)
and an 18-bit output data port (Q0 - Q17). Each input port is
controlled by a free-running Write Clock (WCLK) and a data
input Write Enable pin (
WEN
). Data is written into each array
on every rising clock edge of the appropriate Write Clock
(WCLK) when its corresponding Write Enable line (
WEN
) is
asserted.
FFA
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA
DA
0
-DA
17
HFA
/(
WXOA
)
PAEA
EFA
WCLKB
PAFA
LDA
WENB
DB0-DB17
LDB
• •
WRITE
CONTROL
LOGIC
WRITE
POINTER
INPUT
REGISTER
OFFSET
REGISTER
• •
WRITE
CONTROL
LOGIC
INPUT
REGISTER
OFFSET
REGISTER
•
•
RAM
ARRAY
256 x 18
512 x 18
1024 x 18
•
•
FLAG
LOGIC
READ
POINTER
READ
CONTROL
LOGIC
FLA
WXIA
(
HFA
)/
WXOA
RXIA
RXOA
RSA
WRITE
POINTER
•
•
RAM
ARRAY
256 x 18
512 x 18
1024 x 18
•
•
FLAG
LOGIC
FFB
PAFB
EFB
PAEB
HFB
/
(
WXOB
)
READ
POINTER
READ
CONTROL
LOGIC
EXPANSION
LOGIC
OUTPUT
REGISTER
• •
EXPANSION
LOGIC
OUTPUT
REGISTER
•
•
RESET
LOGIC
RESET
LOGIC
OEA
QA
0
-QA
17
RCLKA
RSB
RXOB
RENA
RXIB
(
HFB
)/
WXOB
WXIB
FLB
OEB
RCLKB
QB
0
-QB
17
RENB
3139 drw 01
The IDT logo is a registered trademark, and SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-839
DECEMBER 1996
DSC-3139/2
5.17
1
IDT72805/72815/72825 CMOS Dual SyncFIFO™
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
The output port of each FIFO bank is controlled by a Read
Clock pin (RCLK) and a Read Enable pin (REN). The Read
Clock can be tied to the Write Clock for single clock operation or
the two clock lines can run asynchronously to one another for
dual clock operation. An Output Enable pin (
OE
) is provided on
the read port of each FIFO for three-state output control.
Each of the two FIFOs has fixed flags, an Empty (
EF
) and a
Full (
FF
). Two kinds of programmable flags, an Almost-Empty
(
PAE
) and an Almost-Full (
PAF
), are provided to improve the
utilization of each FIFO memory bank. The offset loading of the
programmable flags is controlled by a simple state machine and
is initiated by asserting the load pin (
LD
). A Half-Full flag
(
HF
) is available for each FIFO that is implemented as a
single device.
The IDT72805LB/72815LB/72825LB are depth expand-
able using a daisy-chain technique. A set of expansion pins
(XI and XO) are provided for each FIFO. In depth expansion
configuration, FL is grounded on the first device and set high
for all other devices in the daisy-chain.
The IDT72805LB/72815LB/72825LB is fabricated using
IDT's high speed submicron CMOS technology.
PIN CONFIGURATION
PIN 1
A
WCLKA
DA3
DA1
DA0
DB13
DB16
RCLKB
LDB
OEB
DB17
RSB
EFB
GND
QB17
QB16
B
PAFA
FFA
RXOA
QA1
DA4
WENA
WXIA
QA2
DA2
DB12
DB15
RENB
GND
QB15
QB14
C
RXIA
QA0
DA5
DB14
DB11
QB13
QB11
D
FLA
WXOA/
HFA
VCC
DB8
DB10
DB7
VCC
QB12
QB10
QB8
E
QA4
QA3
PAEA
GND
DB9
DB6
VCC
VCC
QB9
QB7
F
QA5
QA6
GND
GND
GND
VCC
GND
QB6
QB5
G
QA7
QA9
VCC
VCC
DA6
DA9
PAEB
DA8
WXOB/
HFB
FLB
DB5
QB3
QB4
QB1
H
QA8
QA10
QA12
VCC
DA7
DA10
QB2
QB0
RXOB
FFB
PAFB
WCLKB
J
QA11
QA13
GND
DA17
GND
DA11
DA14
WXIB
WENB
DB1
RXIB
DB4
K
QA14
QA15
EFA
RSA
OEA
LDA
RENA
RCKLA
DA15
DA12
DB2
L
QA16
QA17
DA16
DA13
DB0
DB3
1
2
3
4
5
6
7
8
9
10
11
3139 drw 02
BGA
(BG 121-1)
TOP VIEW
5.17
2
IDT72805/72815/72825 CMOS Dual SyncFIFO™
256 x 18-BIT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
DA0–DA17
DB0–DB17
Name
Data Inputs
Reset
I/O
I
I
Description
Data inputs for a 18-bit bus.
When
RS
is set LOW, internal read and write pointers are set to the first location of the
RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before
an initial WRITE after power-up.
When
WEN
is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,
if the FIFO is not full.
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition of
WCLK. When
WEN
is HIGH, the FIFO holds the previous data. Data will not be written
into the FIFO if the
FF
is LOW.
RSA
RSB
WCLKA
WCLKB
Write Clock
Write Enable
I
I
WENA
WENB
RCLKA
RCLKB
Read Clock
Read Enable
I
I
When
REN
is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if
the FIFO is not empty.
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of
RCLK. When
REN
is HIGH, the output register holds the previous data. Data will not be
read from the FIFO if the
EF
is LOW.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will
be in a high-impedance state.
RENA
RENB
OEA
OEB
LDA
LDB
FLA
FLB
WXIA
WXIB
RXIA
RXIB
EFA
EFB
PAEA
PAEB
PAFA
PAFB
FFA
FFB
WXOA
/
HFA
WXOB
/
HFB
RXOA
RXOB
QA0–QA17
QB0–QB17
VCC
GND
Output Enable
Load
I
I
First Load
I
In the single device or width expansion configuration,
FL
is grounded. In the depth
expansion configuration,
FL
is grounded on the first device (first load device) and set to
HIGH for all other devices in the daisy chain.
In the single device or width expansion configuration,
WXI
is grounded. In the depth
expansion configuration,
WXI
is connected to
WXO
(Write Expansion Out) of the
previous device.
In the single device or width expansion configuration, RXI is grounded. In the depth
expansion configuration,
RXI
is connected to
RXO
(Read Expansion Out) of the previous
device.
When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited.
When
EF
is HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
When
LD
is LOW, data on the inputs D0–D9 is written to the offset and depth registers
on the LOW-to-HIGH transition of the WCLK, when
WEN
is LOW. When
LD
is LOW,
data on the outputs Q0–Q9 is read from the offset and depth registers on the LOW-to-
HIGH transition of the RCLK, when
REN
is LOW.
Write Expansion
Input
Read Expansion
Input
Empty Flag
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Full Flag
Write Expansion
Out/Half-Full Flag
Read Expansion
Out
Data Outputs
Power
Ground
I
I
O
O
When
PAE
is LOW, the FIFO is almost empty based on the offset programmed into the
FIFO. The default offset at reset is 31 from empty for 72805LB, 63 from empty for
72815LB, and 127 from empty for 72825LB.
O
When
PAF
is LOW, the FIFO is almost full based on the offset programmed into the FIFO.
The default offset at reset is 31 from full for 72805LB, 63 from full for 72815LB, and
127 from full for 72825LB.
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited.
When
FF
is HIGH, the FIFO is not full.
FF
is synchronized to WCLK.
In the single device or width expansion configuration, the device is more than half full
when
HF
is LOW. In the depth expansion configuration, a pulse is sent from
WXO
to
WXI
of the next device when the last location in the FIFO is written.
O
O
O
O
In the depth expansion configuration, a pulse is sent from
RXO
to
RXI
of the next device
when the last location in the FIFO is read.
Data outputs for a 18-bit bus.
8 Vcc pins
9 GND pins
3139 tbl 01
5.17
3
IDT72805/72815/72825 CMOS Dual SyncFIFO™
256 x 18, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
T
BIAS
T
STG
I
OUT
Rating
Terminal Voltage
with respect to GND
Operating
Temperature
Temperature Under
Bias
Storage
Temperature
DC Output Current
Commercial
–0.5 to +7.0
0 to +70
–55 to +125
–55 to +125
50
Unit
V
°C
°C
°C
mA
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
(1)
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.0
—
Typ.
5.0
0
—
—
Max.
5.5
0
—
0.8
Unit
V
V
V
V
3139 tbl 03
NOTE:
3139 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maimum rating conditions for extended
periods may affect reliabilty.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C)
IDT72805LB
IDT72815LB
IDT72825LB
Commercial
t
CLK
= 20, 25, 35ns
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(3)
I
CC2(3)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Average Standby Current (All Input = V
CC
– 0.2V,
except RCLK and WCLK which are free-running)
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max
1
10
—
0.4
250
80
Unit
µA
µA
V
V
mA
mA
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
OE
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
3. Tested at f = 20MHz with outputs unloaded. Icc limits applicable when using both banks of FIFOs simultaneously.
3139 tbl 04
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
10
10
Unit
pF
pF
3139 tbl 05
NOTES:
1. With output deselected, (
OE
= HIGH).
2. Characterized values, not currently tested.
5.17
4
IDT72805/72815/72825 CMOS Dual SyncFIFO™
256 x 18-BIT, 512 x 18, and 1024 x 18
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C)
72805LB20
72815LB20
72825LB20
Min.
Max.
—
2
20
8
8
5
1
5
1
20
12
12
—
0
—
1
—
—
—
—
—
—
8
8
14
14
Low-Z
(2)
50
12
—
—
—
—
—
—
—
—
—
—
35
—
9
9
12
12
30
30
30
12
—
—
—
—
Commercial
72805LB25
72815LB25
72825LB25
Min.
Max.
—
3
25
10
10
6
1
6
1
25
15
15
—
0
—
1
—
—
—
—
—
—
10
10
16
16
40
15
—
—
—
—
—
—
—
—
—
—
40
—
12
12
15
15
35
35
35
15
—
—
—
—
72805LB35
72815LB35
72825LB35
Min.
Max.
—
3
35
14
14
7
2
7
2
35
20
20
—
0
—
1
—
—
—
—
—
—
14
15
18
18
28.6
20
—
—
—
—
—
—
—
—
—
—
45
—
15
15
20
20
40
40
40
20
—
—
—
—
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
HF
t
XO
t
XI
t
XIS
t
SKEW1
t
SKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
(1)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in
Output Enable to Output Valid
Output Enable to Output in High-Z
(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Empty Flag
Clock to Half-Full Flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Set-Up Time
Skew time between Read Clock & Write Clock for
Full Flag
Skew time between Read Clock & Write Clock for
Empty Flag
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3139 tbl 06
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
3139 tbl 07
680
Ω
30pF*
3139 drw 05
Figure 1. Output Load
* Includes jig and scope capacitances.
5.17
5
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