INTEGRATED CIRCUITS
DATA SHEET
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•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4067B
MSI
16-channel analogue
multiplexer/demultiplexer
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
16-channel analogue
multiplexer/demultiplexer
DESCRIPTION
The HEF4067B is a 16-channel analogue
multiplexer/demultiplexer with four address inputs (A
0
to
A
3
), an active LOW enable input (E), sixteen independent
inputs/outputs (Y
0
to Y
15
) and a common input/output (Z).
HEF4067B
MSI
The device contains sixteen bidirectional analogue
switches, each with one side connected to an independent
input/output (Y
0
to Y
15
) and the other side connected to
the common input/output (Z).
With E LOW, one of the sixteen switches is selected (low
impedance ON-state) by A
0
to A
3
. All unselected switches
are in the high impedance OFF-state. With E HIGH all
switches are in the high impedance OFF-state,
independent of A
0
to A
3
.
The analogue inputs/outputs (Y
0
to Y
15
and Z) can swing
between V
DD
as a positive limit and V
SS
as a negative
limit. V
DD
to V
SS
may not exceed 15 V.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF4067BP(N):
HEF4067BD(F):
HEF4067BT(D):
24-lead DIL; plastic
(SOT101-1)
24-lead DIL; ceramic (cerdip)
(SOT94)
24-lead SO; plastic
(SOT137-1)
( ): Package Designator North America
PINNING
Y
0
to Y
15
A
0
to A
3
E
Z
Fig.1 Functional diagram.
independent inputs/outputs
address inputs
enable input (active LOW)
common input/output
Fig.2 Pinning diagram.
January 1995
2
Philips Semiconductors
Product specification
16-channel analogue
multiplexer/demultiplexer
HEF4067B
MSI
Fig.3 Schematic diagram (one switch).
FUNCTION TABLE
INPUTS
E
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
A
3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
A
2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
A
1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
A
0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
CHANNEL
ON
Y
0
−
Z
Y
1
−
Z
Y
2
−
Z
Y
3
−
Z
Y
4
−
Z
Y
5
−
Z
Y
6
−
Z
Y
7
−
Z
Y
8
−
Z
Y
9
−
Z
Y
10
−
Z
Y
11
−
Z
Y
12
−
Z
Y
13
−
Z
Y
14
−
Z
Y
15
−
Z
none
January 1995
3
DSP and ARM Processors
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