DATASHEET
Two Output Differential Buffer for PCIe Gen1 & Gen2
Description
The
ICS9DB102
zero-delay buffer supports PCI Express
clocking requirements. The
ICS9DB102
is driven by a differential
SRC output pair from an ICS CK410/CK505-compliant main
clock. It attenuates jitter on the input clock and has a selectable
PLL Band Width to maximize performance in systems with or
without Spread-Spectrum clocking.
ICS9DB102
Features/Benefits
•
•
•
•
•
•
CLKREQ# pin for outputs 1 and 4/output enable for Express
Card applications
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
Spread Spectrum Compatible/tracks spreading input clock
for low EMI
SMBus Interface/unused outputs can be disabled
Industrial temperature range available
Output Features
•
2 - 0.7V current mode differential output pairs (HCSL)
Key Specifications
•
•
Cycle-to-cycle jitter < 35ps
Output-to-output skew < 25ps
Functional Block Diagram
CLKREQ0#
CLKREQ1#
PCIEX0
CLK_INT
SPREAD
COMPATIBLE
PLL
PCIEX1
C LK_IN C
PLL_BW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV Q 08/27/13
1
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Pin Configuration
PLL_BW
CLK_INT
CLK_INC
vCLKREQ0#
VDD
GND
PCIEXT0
PCIEXC0
VDD
SMBDAT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDDA
GNDA
IREF
vCLKREQ1#
VDD
GND
PCIEXT1
PCIEXC1
VDD
SMBCLK
Power Groups
Note:
Pins preceeded by ' v ' have internal
120K ohm pull down resistors
20-pin SSOP & TSSOP
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PLL_BW
CLK_INT
CLK_INC
vCLKREQ0#
VDD
GND
PCIEXT0
PCIEXC0
VDD
SMBDAT
SMBCLK
VDD
PCIEXC1
PCIEXT1
GND
VDD
vCLKREQ1#
PIN NAME
PIN TYPE
IN
IN
IN
IN
PWR
PWR
OUT
OUT
PWR
I/O
IN
PWR
OUT
OUT
PWR
PWR
IN
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = low, 1= high
True Input for differential reference clock.
Complementary Input for differential reference clock.
Output enable for PCI Expres s output pair 0.
0 = enabled, 1 =disabled
Power supply, nominal 3.3V
Ground pin.
True clock of differential PCI_Express pair.
Complementary clock of differential PCI_Express pair.
Power supply, nominal 3.3V
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
Complementary clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Ground pin.
Power supply, nominal 3.3V
Output enable for PCI Expres s output pair 1.
0 = enabled, 1 =disabled
This pin establishes the reference for the differential current-mode
output pairs. It requires a fixed precision resistor to ground. 475ohm is
the standard value for 100ohm differential impedance. Other
impedances require different values. See data sheet.
Ground pin for the PLL c ore.
3.3V power for the PLL core.
18
19
20
IREF
GNDA
VDDA
ICS9DB102
Pin Number
VDD
GND
5,9,12,16
6,15
9
6
20
19
20
19
Description
PCI Express Outputs
SMBUS
IREF
Analog VDD & GND for PLL core
OUT
PWR
PWR
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV Q 08/27/13
2
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Absolute Max
Symbol
VDDA
VDD
Ts
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Output Supply Voltage
Storage Temperature
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
Max
V
DD
+ 0.5V
V
DD
+ 0.5V
150
115
Units
V
V
C
°C
V
°
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= Tambient; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Tambient
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
Tambcom
Tambind
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Operating Supply Current
Input Frequency
3
Pin Inductance
1
Input Capacitance
1
Clk Stabilization
1,2
Modulation Frequency
Spread Spectrum Modulation
Frequency
OE# Latency
I
DD3.3OP
F
i
L
pin
C
IN
C
OUT
T
STAB
CONDITIONS
Commercial range
Industrial range
3.3 V +/-5%
3.3 V +/-5%
V
IN
= V
DD
V
IN
= 0 V; Inputs with no pull-
up resistors
V
IN
= 0 V; Inputs with pull-up
resistors
Full Active, C
L
= Full load;
all differential pairs tri-stated
V
DD
= 3.3 V
Logic Inputs
Output pin capacitance
From V
DD
Power-Up to 1st
clock
Triangular Modulation
Lexmark Modulation
DIF start after OE# assertion
DIF stop after OE#
deassertion
PLL Bandwidth when
PLL_BW=0
PLL Bandwidth when
PLL_BW=1
@ I
PULLUP
SMBus SDATA pin
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
MIN
0
-40
2
V
SS
- 0.3
-5
-5
-200
75
27
100
100
50
101
7
5
4.5
1.8
30
25
1
400
2
2.7
4
1000
300
500
2.5
33
45
3
1000
3
5.5
0.4
TYP
MAX
70
85
V
DD
+ 0.3
0.8
5
UNITS NOTES
°C
°C
V
V
uA
uA
uA
mA
mA
MHz
nH
pF
pF
ms
kHz
KHz
cycles
KHz
MHz
V
V
mA
ns
ns
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1
1
1
1
1
1
1
99
f
MOD
t
LATOE#
PLL Bandwidth
SMBus Voltage
Low-level Output Voltage
Current sinking at V
OL
= 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
1
2
BW
V
DD
V
OLSMBUS
I
PULLUP
T
RI2C
T
FI2C
Guaranteed by design and characterization, not 100% tested in production.
Time from deassertion until outputs are >200mV
852
REV Q 08/27/13
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
3
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair
T
A
= Tambient; V
DD
= 3.3 V +/-5%; C
L
PARAMETER
SYMBOL
Current Source Output
Zo
Impedance
Voltage High
VHigh
Voltage Low
VLow
Max Voltage
Vovs
Min Voltage
Vuds
Crossing Voltage (abs) Vcross(abs)
Crossing Voltage (var)
Long Accuracy
Average period
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Input to Output Delay
Duty Cycle
Output-to-Output Skew
Jitter, Cycle to cycle
1
2
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω
, I
REF
= 475
Ω
CONDITIONS
MIN
TYP
V
O
= V
x
Statistical measurement on
single ended signal using
Measurement on single ended
signal using absolute value.
3000
660
-150
-300
250
Variation of crossing over all
edges
see Tperiod min-max values
100.00MHz nominal
100.00MHz spread
100.00MHz nominal/spread
V
OL
= 0.175V, V
OH
= 0.525V
V
OH
= 0.525V V
OL
= 0.175V
350
12
9.9970
9.9970
9.8720
175
175
30
30
PLL Mode.
Bypass mode
Measurement from differential
wavefrom
V
T
= 50%
PLL mode. Measurement from
differential wavefrom
Additve Jitter in Bypass Mode
0
3.7
45
MAX
UNITS NOTES
Ω
1
1,3
1,3
1,3
1,3
1,3
1,3
1,2
2
2
1,2
1
1
1
1
1
1
1
1
1
1
850
150
1150
550
140
0
10.0030
10.0533
700
700
125
125
150
4.2
55
25
35
30
mV
mV
mV
mV
ppm
ns
ns
ns
ps
ps
ps
ps
ps
ns
%
ps
ps
ps
d-Vcross
ppm
Tperiod
Tabsmin
t
r
t
f
d-t
r
d-t
f
t
pd
t
pdbyp
d
t3
t
sk3
t
jcyc-cyc
t
jcyc-cycbyp
.
Guaranteed by design, not 100% tested in production.
The 9DB102 does not add a ppm error to the input clock
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV Q 08/27/13
4
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Electrical Characteristics - PLL Parameters
T
A
= Tambient; Supply Voltage V
DD
= 3.3 V +/-5%
Group
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Parameter
j
peak-hibw
j
peak-lobw
pll
HIBW
pll
LOBW
Description
(PLL_BW = 1)
(PLL_BW = 0)
(PLL_BW = 1)
(PLL_BW = 0)
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=1)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
Min
0
0
2
0.4
Typ
1
1
2.5
0.5
40
2.7
Max
2.5
2
3
1
108
3.1
Units
dB
dB
MHz
MHz
ps
ps rms
Notes
1,4
1,4
1,5
1,5
1,2,3
1,2,3
Jitter, Phase
t
jphasePLL
2.2
1.3
3.1
3
ps rms
ps rms
1,2,3
1,2,3
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
3. Device driven by 932S421BGLF or equivalent
4.
Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5.
Measured at 3 db dow n or half pow er point.
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV Q 08/27/13
5
Embedded System
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