STLVDS9637BD datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Analog mixed-signal IC> Drivers and interfaces> STLVDS9637BD

STLVDS9637BD: DescriptionDUAL LINE RECEIVER, PDSO8, SO-8; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size275KB，13 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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STLVDS9637BD Overview

DUAL LINE RECEIVER, PDSO8, SO-8

STLVDS9637BD Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	SOIC
package instruction	SO-8
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Differential output	NO
Input properties	DIFFERENTIAL
Interface integrated circuit type	LINE RECEIVER
Interface standards	EIA-644; TIA-644; EIA-422-B; TIA-422-B
JESD-30 code	R-PDSO-G8
JESD-609 code	e4
length	4.9 mm
Humidity sensitivity level	1
Number of functions	2
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output low current	0.008 A
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum receive delay	3.3 ns
Number of receiver bits	2
Maximum seat height	1.75 mm
Maximum slew rate	10 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm

STLVDS9637BD Preview

STLVDS32

HIGH SPEED

DIFFERENTIAL LINE RECEIVERS

MEETS OR EXCEEDS THE

REQUIREMENTS OF ANSI TIA/EIA-644

STANDARD

OPERATES WITH A SINGLE 3.3V SUPPLY

DESIGNED FOR SIGNALING RATE UP TO

400Mbps

DIFFERENTIAL INPUT THRESHOLDS

±100mV

MAX

TYPICAL PROPAGATION DELAY TIME OF

2.5ns

POWER DISSIPATION 60mW TYPICAL PER

RECEIVER AT 200MHz

LOW VOLATGE TTL (LVTTL) LOGIC

OUTPUT LEVELS

PIN COMPATIBLE WITH THE AM26LS32,

SN65LVD32

OPEN CIRCUIT FAIL SAFE

ESD PROTECTION:

7KV RECEIVER PINS

3KV ALL PINS VS GND

SOP

TSSOP

DESCRIPTION

The STLVDS32 is a differential line receiver that

implements the electrical characteristics of low

voltage differential signaling (LVDS). This

signaling technique lowers the output voltage

levels of 5V differential standard levels (such as

TIA/EIA-422B) to reduce the power, increase the

switching speeds and allow operations with a 3.3V

supply rail. This differential receiver provides a

ORDERING CODES

Type

STLVDS32BD

STLVDS32BDR

STLVDS32BTR

Temperature

Range

-40 to 85 °C

valid logical output state with a 3.3V supply rail. It

also provides a valid logical output state with a

±100mV

differential input voltage within the input

common mode voltage range. The input common

mode voltage allows 1V of ground potential

difference between two LVDS nodes.

The intended application of this device and

signalling technique is both point-to-point and

multidrop data transmission over controlled

impedance media approximately 100Ω. The

transmission media may be printed circuit board

traces, backplanes or cables. The ultimate rate

and distance of data transfer depend upon the

attenuation characteristics of the media and noise

coupling to the environment.

The STLVDS32 version is characterized for

operation from -40°C to 85°C.

Package

SO-16 (Tube)

SO-16 (Tape & Reel)

TSSOP16 (Tape & Reel)

Comments

50parts per tube / 20tube per box

2500 parts per reel

September 2003

1/13

STLVDS32

PIN CONFIGURATION

PIN DESCRIPTION

PlN N°

2, 6, 10, 14

1, 7, 9, 15

3, 5, 11, 13

SYMBOL

1A to 4A

1B to 4B

1Y to 4Y

GND

NAME AND FUNCTION

Receiver Inputs

Negated Receiver Inputs

Receiver Outputs

Enable

Ground

Supply Voltage

LOGIC DIAGRAM AND LOGIC SYMBOL

2/13

STLVDS32

TRUTH TABLE

DIFFERENTIAL INPUTS

A, B

≥

100mV

-100mV < V

< 100mV

≤

-100mV

OPEN

ENABLES

OUTPUT

L = Low level, H = High Level, X = Don’t care, Z = High Impedance,? = Indeterminate

ABSOLUTE MAXIMUM RATINGS

Symbol

ESD

stg

Supply Voltage (Note 1)

Input Voltage

Input Voltage (A or B inputs)

Human Body Model

Storage Temperature Range

Pins Receivers

All Pins vs GND

Parameter

Value

-0.5 to 4.6

-0.5 to (V

+ 0.5)

-0.5 to 4.6

-65 to +150

Unit

°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is

not implied.

Note 1: All voltages except differential I/O bus voltage, are with respect to the network ground terminal.

RECOMMENDED OPERATING CONDITIONS

Symbol

Supply Voltage

HIGH Level Input Voltage (ENABLE)

LOW Level Input Voltage (ENABLE)

Magnitude of Differential Input Voltage

Common Mode Input Voltage

Operating Temperature Range

0.1

0.5|V

-40

Parameter

Min.

3.0

2.0

0.8

0.6

2.4-0.5|V

- 0.8

°C

Typ.

3.3

Max.

3.6

Unit

3/13

STLVDS32

ELECTRICAL CHARACTERISTICS

(Over recommended operating conditions unless otherwise noted.

All typical values are at T

= 25°C, and V

= 3.3V)

Symbol

ITH+

ITH-

I(OFF)

Parameter

Positive Going Differential

Input Voltage Threshold

Negative Going Differential

Input Voltage Threshold

High Level Output Voltage

Low Level Output Voltage

Supply Current

Test Conditions

Min.

Typ.

Max.

100

-100

= -8mA

= -4mA

= 8mA

0.25

-10

-3

µA

Enabled, No Load

Disabled

Input Current (A or B inputs) V

= 0V

= 2.4V

Power off Input Current (A

or B inputs)

High Level Input Current

(EN, G, G or Inputs)

Low Level Input Current

(EN, G, G or Inputs)

High Impedance Output

Current

= 0

= 2V

= 0.8V

= 0 or V

= 3.6V

2.4

2.8

0.4

0.5

-20

µA

Unit

-2

-1.2

4/13

STLVDS32

SWITCHING CHARACTERISTICS

(Unless otherwise noted. Typical values are referred to T

= 25°C

and V

= 3.3V)

Symbol

PLH

PHL

sk(O)

sk(P)

sk(PP)

PZH

Parameter

Propagation Delay Time,

= 10pF

Low to High Output

Propagation Delay Time,

High to Low Output

Differential Output Signal

Rise Time

Differential Output Signal

Fall Time

Channel to Channel Output

Skew (note1)

Pulse Skew (|t

PHL

- t

PLH

(note2)

Part to Part Skew (note3)

Propagation Delay Time,

High Impedance to High

Level Output

Propagation Delay Time,

High Impedance to Low

Level Output

Propagation Delay Time,

High Level to High

Impedance Output

Propagation Delay Time,

Low Level to High

Impedance Output

Fig. 2

Test Conditions

Fig. 1

Min.

1.5

Typ.

2.5

0.4

0.1

0.2

0.3

0.4

Max.

3.3

Unit

PZL

PHZ

PLZ

Note 1: t

sk(O)

is the maximum delay time difference between the propagation delay of one channel and that of the others on the same chip

with any event on the inputs.

Note 2: t

sk(P)

is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge

of the same channel.

Note 3: t

sk(PP)

is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same

, and within 5°C of each other within the operating temperature range.

5/13

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