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UT54ACS193-UCA

Description
Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, CDFP16, BOTTOM-BRAZED, CERAMIC, DFP-16
Categorylogic    logic   
File Size102KB,8 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

UT54ACS193-UCA Overview

Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, CDFP16, BOTTOM-BRAZED, CERAMIC, DFP-16

UT54ACS193-UCA Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCobham PLC
package instructionBOTTOM-BRAZED, CERAMIC, DFP-16
Reach Compliance Codeunknown
Other featuresTCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
Counting directionBIDIRECTIONAL
seriesAC
JESD-30 codeR-CDFP-F16
JESD-609 codee0
Load/preset inputYES
Logic integrated circuit typeBINARY COUNTER
Maximum Frequency@Nom-Sup56000000 Hz
MaximumI(ol)0.0001 A
Operating modeSYNCHRONOUS
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL16,.3
Package shapeRECTANGULAR
Package formFLATPACK
power supply5 V
propagation delay (tpd)24 ns
Certification statusNot Qualified
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
Trigger typePOSITIVE EDGE
width6.731 mm
UT54ACS193/UT54ACTS193
Radiation-Hardened
Synchronous 4-Bit Up-Down Dual Clock Counters
FEATURES
Look-ahead circuitry enhances cascaded counters
Fully synchronous in count modes
Asynchronous clear
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
16-pin DIP
-
DESCRIPTION
The UT54ACS193 and the UT54ACTS193 are synchronous 4-
operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each
output counting spikes normally associated with asynchronous
counters.
level transition of either count input (Up or Down). The direc-
tion of the counting is determined by which count input is pulsed
PINOUTS
Top View
B
Q
B
Q
A
DOWN
UP
Q
C
Q
D
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
A
CLR
BO
CO
LOAD
C
D
16-Lead Flatpack
B
Q
B
Q
A
DOWN
UP
Q
C
Q
D
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
A
CLR
BO
CO
LOAD
C
D
FUNCTION TABLE
FUNCTION
The counters are fully programmable. The outputs may be pre-
set to either level by placing a low on the load input and entering
agree with the data inputs independently of the count pulses.
Asynchronous loading allows the counters to be used as modu-
preset inputs.
A clear input has been provided that forces all outputs to the low
pendent of the count and the load inputs.
The counter is designed for efficient cascading without the need
BO) produces a low-
Similarly, the carry output (CO
while the count is maximum
CLOCK
UP
CLOCK
DOWN
H
CLR
L
L
LOAD
H
H
X
L
Count Up
Count Down
Reset
Load Preset
Input
H
X
X
X
X
H
L
137
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Index Files: 1996  319  2207  1331  2815  41  7  45  27  57 
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