Integrated
Circuit
Systems, Inc.
ICS9DB801
Eight Output Differential Buffer for PCI Express (50-200MHz)
Recommended Application:
DB800 Version 2.0 Yellow Cover part with PCI Express
suppor with extended bypass mode frequency range.
Output Features:
•
8 - 0.7V current-mode differential output pairs
•
Supports zero delay buffer mode and fanout mode
•
Bandwidth programming available
Key Specifications:
•
Outputs cycle-cycle jitter < 50ps
•
Outputs skew: 50ps
•
50 - 200MHz operation
•
Extended frequency range in bypass mode:
Revision B: up tp 333.33 MHz
Revision C: up to 400 MHz
Features/Benefits:
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
•
•
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Supports polarity inversion to the output enables ,
SRC_STOP and PD.
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE0#
OE3#
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE1#
OE2#
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
LOCK
OE7#
OE4#
DIF_7
DIF_7#
OE_INV
VDD
DIF_6
DIF_6#
OE6#
OE5#
DIF_5
DIF_5#
GND
VDD
DIF_4
DIF_4#
HIGH_BW#
SRC_STOP
PD
GND
Pin Configurations
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
LOCK
OE_7
OE_4
DIF_7
DIF_7#
OE_INV
VDD
DIF_6
DIF_6#
OE_6
OE_5
DIF_5
DIF_5#
GND
VDD
DIF_4
DIF_4#
HIGH_BW#
SRC_STOP#
PD#
GND
OE_INV = 0
Polarity Inversion Pin List Table
OE_INV
Pins
6
7
14
15
26
27
35
36
43
44
0
OE_0
OE_3
OE_1
OE_2
PD#
SRC_STOP#
OE_5
OE_6
OE_4
OE_7
1
OE0#
OE3#
OE1#
OE2#
PD
SRC_STOP
OE5#
OE6#
OE4#
OE7#
OE_INV = 1
48-pin SSOP & TSSOP
1015B—09/07/06
ICS9DB801
ICS9DB801
(Same as ICS9DB108)
Integrated
Circuit
Systems, Inc.
ICS9DB801
Pin Desription for OE_INV = 0
PIN
PIN # PIN NAME
TYPE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
IN
PWR
PWR
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
I/O
DESCRIPTION
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
Power supply, nominal 3.3V
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
1015B—09/07/06
2
Integrated
Circuit
Systems, Inc.
ICS9DB801
Pin Desription for OE_INV = 0
PIN
PIN # PIN NAME
TYPE
25 GND
PWR
Ground pin.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PD#
SRC_STOP#
HIGH_BW#
DIF_4#
DIF_4
VDD
GND
DIF_5#
DIF_5
OE_5
OE_6
DIF_6#
DIF_6
VDD
OE_INV
DIF_7#
DIF_7
OE_4
OE_7
LOCK
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
IN
OUT
OUT
IN
IN
OUT
DESCRIPTION
Asynchronous active low input pin, with 120Kohm internal pull-
up resistor, used to power down the device. The internal clocks
are disabled and the VCO and the crystal are stopped.
Active low input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
46
47
48
IREF
GNDA
VDDA
IN
PWR
PWR
1015B—09/07/06
3
Integrated
Circuit
Systems, Inc.
ICS9DB801
Pin Desription for OE_INV = 1
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE0#
OE3#
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE1#
OE2#
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
PIN TYPE
IN
PWR
PWR
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
I/O
DESCRIPTION
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
Power supply, nominal 3.3V
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
1015B—09/07/06
4
Integrated
Circuit
Systems, Inc.
ICS9DB801
Pin Desription for OE_INV = 1
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PIN NAME
GND
PD
SRC_STOP
HIGH_BW#
DIF_4#
DIF_4
VDD
GND
DIF_5#
DIF_5
OE5#
OE6#
DIF_6#
DIF_6
VDD
OE_INV
DIF_7#
DIF_7
OE4#
OE7#
LOCK
PIN TYPE
PWR
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
IN
OUT
OUT
IN
IN
OUT
Ground pin.
Asynchronous active high input pin used to power down the
device. The internal clocks are disabled and the VCO is stopped.
Active high input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
3.3V output indicating PLL Lock Status. This pin goes high when
lock is achieved.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
DESCRIPTION
46
47
48
IREF
GNDA
VDDA
IN
PWR
PWR
1015B—09/07/06
5
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