PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87973I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
F
EATURES
•
Fully integrated PLL
•
14 LVCMOS outputs; (12) clock, (1) feedback, (1) sync
•
Selectable LVCMOS or LVPECL clock inputs
•
CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
PCLK, nPCLK pair supports the following input types:
LVPECL, CML, SSTL
•
Output frequency: 125MHz
•
Output skew: 550ps (maximum)
•
Cycle-to-cycle jitter: ±100ps (typical)
•
PLL reference zero delay: TBD
•
Full 3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Pin compatible with MPC973
•
Compatible with PowerPC™ and Pentium™ Microprocessors
G
ENERAL
D
ESCRIPTION
The ICS87973I is a low voltage, low skew,
LVCMOS clock generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS87973I has two se-
lectable clock inputs. The CLK0, CLK1 inputs
accept LVCMOS or LVTTL input levels. The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels.
,&6
P
IN
A
SSIGNMENT
EXT_FB
GNDO
GNDO
GNDO
V
DDO
V
DDO
QB0
QB1
QB2
QB3
QFB
V
DD
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
V
DDO
QA2
GNDO
QA1
V
DDO
QA0
GNDO
VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
42
43
44
45
46
47
48
49
50
51
52
1
GNDI
FSEL_FB0
FSEL_FB1
QSYNC
GNDO
QC0
V
DDO
QC1
FSEL_C0
FSEL_C1
QC2
V
DDO
QC3
GNDO
INV_CLK
25
24
23
22
21
ICS87973I
20
19
18
17
16
15
14
2
nMR/OE
3
FRZ_CLK
4
FRZ_DATA
5 6
FSEL_FB2
PLL_SEL
7 8
REF_SEL
CLK_SEL
9 10 11 12 13
CLK0
CLK1
PCLK
nPCLK
V
DDA
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87973BYI
www.icst.com/products/hiperclocks.html
1
REV. A MAY 28, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87973I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
Type
Description
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs. When
LOW, resets the outputs to tristate and resets output divide circuitr y.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
Clock input for freeze circuitr y.
Configuration data input for freeze circuitr y.
Select pins control Feedback Divide value.
Selects between the PLL and reference clocks as the input to the output
dividers. When HIGH, selects PLL. When LOW, bypasses the PLL.
LVCMOS / LVTTL interface levels.
Selects between CLK0 and LVPECL clock inputs. When HIGH, selects
LVPECL. When LOW, selects CLK0. LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 or CLK1 as phase detector
reference. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
Reference clock inputs. LVCMOS / LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5, 26, 27
Name
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
PLL_SEL
REF_SEL
CLK_SEL
CLK0,
CLK1
PCLK
nPCLK
V
DDA
INV_CLK
GNDO
QC3, QC2,
QC1, QC0
V
DDO
QSYNC
V
DD
QFB
EXT_FB
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
VCO_SEL
Power
Input
Input
Input
Input
Pullup
Pullup
Pullup
Pullup
6
7
8
9, 10
11
12
13
14
15, 24, 30,
35, 39, 47, 51
16, 18,
21, 23
17, 22, 33,
37, 45, 49
25
28
29
31
32, 34,
36, 38
40, 41
42, 43
44, 46,
48, 50
52
Input
Input
Input
Input
Input
Input
Power
Input
Power
Output
Power
Output
Power
Output
Input
Output
Input
Input
Output
Input
Pullup
Pullup
Pullup
Pullup
Pulldown Non-inver ting differential LVPECL clock input.
Pullup
Inver ting differential LVPECL clock input.
Analog supply pin.
Pullup
Inver ted clock select for QC2 and QC3 outputs.
Power supply ground.
Bank C clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins.
See Figure 1, Timing Diagrams.
Positive supply pins.
Feedback clock output.
Pullup
Extended feedback. LVCMOS / LVTTL interface levels.
Bank B clock outputs.7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Pullup
Pullup
Selects pins for Bank B outputs.
Selects pins for Bank A outputs.
Bank A clock outputs.7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1.
When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
87973BYI
www.icst.com/products/hiperclocks.html
4
REV. A MAY 28, 2002
Embedded System
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