EEWORLDEEWORLDEEWORLD

Part Number

Search

MPC973FA

Description
PLL Based Clock Driver, 973 Series, 12 True Output(s), 0 Inverted Output(s), PQFP52, LQFP-52
Categorylogic    logic   
File Size630KB,13 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

MPC973FA Overview

PLL Based Clock Driver, 973 Series, 12 True Output(s), 0 Inverted Output(s), PQFP52, LQFP-52

MPC973FA Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionLQFP,
Contacts52
Reach Compliance Codecompliant
series973
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-PQFP-G52
JESD-609 codee0
length10 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals52
Actual output times12
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.55 ns
Maximum seat height1.7 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width10 mm

MPC973FA Preview

DATA SHEET
MOTOROLA
Low Voltage PLL Clock Driver
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC973/D
Rev. 2, 09/2001
MPC973
Low Voltage PLL Clock Driver
The MPC973 is a 3.3 V compatible, PLL based clock driver device
targeted for high performance CISC or RISC processor based systems.
With output frequencies of up to 125 MHz and skews of 550 ps the MPC973
is ideally suited for most synchronous systems. The device offer twelve low
skew outputs plus a feedback and sync output for added flexibility and ease
of system implementation.
Fully Integrated PLL
Output Frequency up to 125 MHz
Compatible with PowerPC and Pentium Microprocessors
LQFP Packaging
3.3 V V
CC
• ±
100ps Typical Cycle–to–Cycle Jitter
LOW VOLTAGE
PLL CLOCK DRIVER
Freescale Semiconductor, Inc...
The MPC973 features an extensive level of frequency programmability
between the 12 outputs as well as the input vs output relationships. Using
the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2,
5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock
edge prior to the coincident edges of the Qa and Qc outputs. The Sync
output will indicate when the coincident rising edges of the above
relationships will occur. The selectability of the feedback frequency is
independent of the output frequencies, this allows for very flexible
programming of the input reference vs output frequency relationship. The
output frequencies can be either odd or even multiples of the input
SCALE 2:1
reference. In addition the output frequency can be less than the input
FA SUFFIX
frequency for applications where a frequency needs to be reduced by a
52–LEAD LQFP PACKAGE
non–binary factor. The Power–On Reset ensures proper programming if the
CASE 848D-03
frequency select pins are set at power up. If the fselFB2 pin is held high, it
may be necessary to apply a reset after power–up to ensure
synchronization between the QFB output and the other outputs. The internal
power–on reset is designed to provide this function, but with power–up
conditions being dependent, it is difficult to guarantee. All other conditions of
the fsel pins will automatically synchronize during PLL lock acquisition.
The MPC973 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug as
well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines. The
MPC973 allows for the enabling of each output independently via a serial input port. When disabled or “frozen” the outputs will be
locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen” the outputs will
activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only
when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A power-on reset will ensure
that upon power up all of the outputs will be active. Note that all of the control inputs on the MPC973 have internal pull–up resistors.
The MPC973 is fully 3.3 V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL
compatible levels while the outputs provide LVCMOS levels with the capability to drive 50
transmission lines. For series
terminated lines each MPC973 output can drive two 50
lines in parallel thus effectively doubling the fanout of the device.
The MPC973 can consume significant power in some configurations. Users are encouraged to review Application Note
AN1545/D in the Advanced Clock Drivers Device Data book (DL207/D) for a discussion on the thermal issues with the MPC family
of clock drivers.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
IDT™
Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
1
MPC973
MPC973
Low Voltage PLL Clock Driver
NETCOM
MPC973
Freescale Semiconductor, Inc.
fselFB0
27
26
25
24
23
22
21
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GNDO
Inv_Clk
20
19
18
17
16
15
14
1
2
3
4
5
6
7
8
9
10
11
12
13
VCCA
fselc0
0
1
0
1
Ext_FB
GNDO
GNDO
GNDO
VCCO
VCCO
VCCI
28
PCLK
QFB
29
PCLK
Qb0
Qb1
Qb2
Qb3
32
39
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
40
41
42
43
44
45
46
47
48
49
50
51
52
38
37
36
35
34
33
31
30
MPC973
Freescale Semiconductor, Inc...
GNDO
Qa1
VCCO
Qa0
GNDO
VCO_Sel
Ref_Sel
TClk_Sel
fselFB2
MR/OE
GNDI
TClk0
Frz_Data
All inputs have internal pull-up resistors (appr. 50 K) except for the xtal1 and xtal2 pins.
Figure 1. 52–Lead Pinout
(Top View)
FUNCTION TABLE 1
fsela1
0
0
1
1
fsela0
0
1
0
1
Qa
÷4
÷6
÷8
÷12
fselb1
0
0
1
1
fselb0
0
1
0
1
Qb
÷4
÷6
÷8
÷10
fselc1
0
0
1
1
Qc
÷2
÷4
÷6
÷8
FUNCTION TABLE 2
*fselFB2
0
0
0
0
fselFB1
0
0
1
1
fselFB0
0
1
0
1
QFB
÷4
÷6
÷8
÷10
PLL_EN
Frz_Clk
FUNCTION TABLE 3
Control Pin
VCO_Sel
Ref_Sel
TCLK_Sel
PLL_En
MR/OE
Inv_Clk
Logic ‘0’
VCO/2
TCLK
TCLK0
Bypass PLL
Master Reset/Output Hi–Z
Non–Inverted Qc2, Qc3
Logic ‘1’
VCO
Xtal (PECL)
TCLK1
Enable PLL
Enable Outputs
Inverted Qc2, Qc3
1
0
0
÷8
1
0
1
÷12
1
1
0
÷16
1
1
1
÷20
* If the fselFB2 is 1, it may be necessary to apply a reset after power up
to ensure synchronization between QFB and the other inputs.
IDT™
Low Voltage PLL Clock Driver
TClk1
For More Information On This Product,
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Go to: www.freescale.com
2
2
MPC973
MOTOROLA
MPC973
Low Voltage PLL Clock Driver
NETCOM
Freescale Semiconductor, Inc.
PCLK
PCLK
MPC973
VCO_Sel
PLL_En
REF_SEL
Sync
Frz
Qa0
Qa1
Qa2
Qa3
D Q
Sync
Frz
Qb0
Qb1
Qb2
Qb3
fselFB2
TCLK0
TCLK1
TCLK_Sel
Ext_FB
0
1
PHASE
DETECTOR
LPF
VCO
0
1
D Q
Freescale Semiconductor, Inc...
MR/OE
POWER ON
RESET
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
fsela0:1
fselb0:1
fselc0:1
fselFB0:1
2
2
2
2
Sync Pulse
Data Generator
÷4, ÷6, ÷8, ÷10
0
1
D Q
Sync
Frz
D Q
Sync
Frz
Qc0
Qc1
Qc2
Qc3
QFB
÷2
D Q
D Q
Sync
Frz
QSync
Frz_Clk
Frz_Data
Inv_Clk
Output Disable
Circuitry
12
Figure 2. Logic Diagram
IDT™
Low Voltage PLL Clock Driver
For More Information On This Product,
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Go to: www.freescale.com
MOTOROLA
3
MPC973
3
MPC973
Low Voltage PLL Clock Driver
NETCOM
MPC973
fVCO
Freescale Semiconductor, Inc.
1:1 Mode
Qa
Qc
Sync
2:1 Mode
Qa
Qc
Sync
3:1 Mode
Qc(÷2)
Freescale Semiconductor, Inc...
Qa(÷6)
Sync
3:2 Mode
Qa(÷4)
Qc(÷6)
Sync
4:1 Mode
Qc(÷2)
Qa(÷8)
Sync
4:3 Mode
Qa(÷6)
Qc(÷8)
Sync
6:1 Mode
Qa(÷12)
Qc(÷2)
Sync
Figure 3. Timing Diagrams
IDT™
Low Voltage PLL Clock Driver
For More Information On This Product,
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Go to: www.freescale.com
4
4
MPC973
MOTOROLA
MPC973
Low Voltage PLL Clock Driver
NETCOM
Freescale Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Symbol
V
CC
V
I
I
IN
T
Stor
Supply Voltage
Input Voltage
Input Current
Storage Temperature Range
–40
Parameter
Min
–0.3
–0.3
Max
4.6
V
CC
+ 0.3
±20
125
MPC973
Unit
V
V
mA
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
THERMAL CHARACTERISTICS
Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive
capability products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die
power, the corresponding die temperature and the relationship to longterm reliability is addressed in the Motorola application note
AN1545.
DC CHARACTERISTICS
(Note 4.; T
A
= 0° to 70°C; V
CC
= 3.3 V
±5%)
Symbol
V
CCA
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
I
IN
I
CC
I
CCA
C
IN
C
pd
Characteristic
Analog V
CC
Voltage
Input HIGH Voltage
Input LOW Voltage
Peak–to–Peak Input Voltage
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
Maximum Quiescent Supply Current
Analog V
CC
Current
Input Capacitance
Power Dissipation Capacitance
25
190
15
PCLK
PCLK
300
V
CC
–2.0
2.4
0.5
±120
215
20
4
Min
2.935
2.0
Typ
Max
V
CC
3.6
0.8
1000
V
CC
–0.6
V
V
µA
mA
mA
pF
pF
Per Output
Unit
V
V
V
mV
Note 1.
I
OH
= –20 mA (Note 2.)
I
OL
= 20 mA (Note 2.)
Note 3.
All VCC PIns
Condition
Freescale Semiconductor, Inc...
1. V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the
V
CMR
range and the input lies within the V
PP
specification.
2. The MPC973 outputs can drive series or parallel terminated 50
(or 50
to V
CC
/2) transmission lines on the incident edge (see Applications
Info section).
3. Inputs have pull–up/pull–down resistors which affect input current.
4. Special thermal handling may be required in some configurations.
PLL INPUT REFERENCE CHARACTERISTICS
(T
A
= 0° to 70°C)
Symbol
t
r
, t
f
f
ref
f
refDC
Characteristic
TCLK Input Rise/Falls
Reference Input Frequency
Reference Input Duty Cycle
Note 5.
25
Min
Max
3.0
100
Note 5.
75
Unit
ns
MHz
%
Note 5.
Condition
5. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100MHz, minimum input reference frequency
is limited by the VCO lock range and the feedback divider.
IDT™ Low Voltage PLL Clock Driver
For More Information On This Product,
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Go to: www.freescale.com
MOTOROLA
5
MPC973
5
ce6.0->ce5.0 application issues
Can WINCE6.0's cetsc.exe be used on WINCE5.0? If so, what are the conditions required?...
xiaomi_1981 Embedded System
MCU Application Programming Skills (FAQ) 1
1. What are the advantages and disadvantages of C language and assembly language when developing single-chip microcomputers? Answer: Assembly language is a symbolic language that uses text mnemonics t...
songbo MCU
I have some questions about the programming of the input mode of the Renesas microcontroller I/O. I would like some advice from an expert!
[i=s] This post was last edited by paulhyde on 2014-9-15 03:31 [/i] I connected a button to P03 and want to use it to trigger an action, as follows: I set the I/O mode of P0.3 to IN main() { P13.0=1; ...
zhangyaojianll Electronics Design Contest
When collecting a row of data and putting it into FIFO, should the clock remain unchanged when reading data from FIFO?
When doing image interpolation, converting 720P to 1080p, I want to collect data one line and put it into FIFO. So when reading data from FIFO, should the clock remain unchanged? eeworldpostqq...
桂花蒸 FPGA/CPLD
How can the serial port communicate with the board?
I would like to ask, there is a VGA interface on my board, how can I use the serial port on the computer to communicate with the VGA interface, and what kind of board do I need to convert the communic...
小庞 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2896  2238  1625  205  1858  59  46  33  5  38 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号