It
8 BIT SINGLE CHIP MICROCONTROLLER
Preliminary
LC875780A/72A
LC875780A
8-Bit Single Chip Microcontroller incorporating 80K-byte ROM and 3K-byte RAM on chip.
LC875772A
8-Bit Single Chip Microcontroller incorporating 72K-byte ROM and 3K-byte RAM on chip.
Overview
The LC875780A,LC875772A is 8-bit single chip microcontroller with the following one-chip features:
- CPU : Operable at a minimum bus cycle time of 100ns
- On-chip ROM Maximum Capacity : LC875780A 80K bytes
LC875772A 72K bytes
- On-chip RAM Capacity : 3K bytes
- two high performance 16-bit timer/counters (can be divided into 8 bit timers)
- four 8-bit timers with prescalers
- timer for use as date/time clock
- one synchronous serial I/O port (with automatic block transmit/receive function)
- one asynchronous/synchronous serial I/O port
- 12-bit PWM × 2
- 12-channel × 8-bit AD converter
- high speed 8-bit parallel interface
- high speed clock counter
- system clock divider
- 20-source 10-vectored interrupt system
Features
(1) Read Only Memory (ROM)
- 81920 × 8 bits (LC875780A)
- 73728 × 8 bits (LC875772A)
(2) Random Access Memory (RAM) : 3072 × 9 bit
♦
No products described or contained herein are intended for use in surgical implants, life-support systems,
aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the
like, the failure of which may directly or indirectly cause injury, death or property loss.
♦
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
1) Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates,
subsidiaries and distributors and all their officers and employees, jointly and severally, against any
and all claims and litigation and all damages, cost and expenses associated with such use:
2) Not impose any responsibility for any fault or negligence which may be cited in any such claim or
litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of
their officers and employees jointly or severally.
♦
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no
guarantees are made or implied regarding its use or any infringements of intellectual property rights or other
rights of third parties.
This catalog provides information as of Apr 2002. Specifications and information herein are subject to change
without notice.
SANYO Electric Co., Ltd. Semiconductor Company. System-Business Div.
1-1-1, Sakata Oizumi-Machi, Gunma, JAPAN
Ver.1.00
Apr 03 Microcomputer Business Unit T.Kitamura
1/27
LC875780A/72A
(3) Bus Cycle Time
- 100ns (10MHz)
Note: Bus cycle time indicates the speed to read ROM.
(4) Minimum Instruction Cycle Time : 300ns (10MHz)
(5) Ports
- Input/output ports
Input/output programmable for each bit individually
Data direction programmable in nibble units
- Input ports
- PWM output ports
- Oscillator pins
- Reset pin
- Power supply
43 (P1n, P2n, P70 to P73, P8n, PAn, PBn, PCn)
8 (P0n)
2 (XT1, XT2)
2 (PWM0, PWM1)
2 (CF1, CF2)
1 (
RES
)
6 (VSS1 to 3, VDD1 to 3)
(6) Timer
- Timer 0 : 16-bit timer/counter with capture register
Mode 0: Two 8-bit timers with programmable 8-bit prescaler and 8-bit capture register
Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit
counter with 8-bit capture register
Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register
Mode 3: 16-bit counter with 16-bit capture register
- Timer 1 : PWM/16-bit timer/counter with toggle output
Mode 0: 8-bit timer (with toggle output) + 8-bit timer/counter (with toggle output)
Mode 1: Two 8-bit PWM
Mode 2: 16-bit timer/counter (with toggle output) Toggle output is also possible by using the
lower order 8 bits.
Mode 3: 16 bit timer (with toggle output) The lower order 8 bits can be used as PWM output.
- Timer 4:
- Timer 5:
- Timer 6:
- Timer 7:
8-bit timer with 6-bit prescaler
8-bit timer with 6-bit prescaler
8-bit timer with 6-bit prescaler
8-bit timer with 6-bit prescaler
- Base timer
1. Clock for the base timer is selectable from sub-clock (32.768kHz crystal oscillation), system
clock or programmable prescaler output of timer 0.
2. There can be five separate interrupt sources.
(7) High speed clock counter
1. Maximum of 20MHz possible (when using a 10MHz main clock).
2. Real-time output
(8) Serial interface
- SIO 0: 8 bit synchronous serial interface
1. LSB first/MSB first-function available
2. An internal 8-bit baud-rate generator (maximum transmit clock period 4/3 T
CYC
)
3. Consecutive automatic data communication (1 - 256 bits)
- SIO 1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 T
CYC
)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud-rate 8 - 2048 T
CYC
)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 T
CYC
)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
2/27
Ver.1.00
LC875780A/72A
(9) AD converter
- 12-channel × 8-bit AD converter
(10) PWM
- 2 channel × synchronous variable 12 bit PWM
(11) Parallel interface
- RS, RD , WR , CS0 outputs (polarity can be toggled)
- read/write possible in 1 T
CYC
(12) Remote receiver circuit (share with P73/INT3/T0IN terminal)
- Noise rejection function (The filtering time of the noise rejection filter (1T
CYC
/32 T
CYC
/128 T
CYC
) can be
switched by program.)
(13) Watchdog timer
- External RC circuit is required.
- Interrupt or system reset is activated when the timer overflows.
(14) Interrupts
- 20-source and 10-vectored interrupt function:
1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level
nesting possible. During interrupt handling, an equal or lower level interrupt request is refused.
2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt
takes precedence. In the case of equal priority levels, the vector with the lowest address takes
precedence.
No.
Vector
Selectable
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt signal
1
00003H
INT0
2
0000BH
INT1
3
00013H
INT2/T0L/INT4
4
0001BH
INT3/INT5/Base timer
5
00023H
T0H
6
0002BH
T1L/T1H
7
00033H
SIO0
8
0003BH
SIO1
9
00043H
ADC/T6/T7
10
0004BH
Port 0/T4/T5/PWM0, PWM1
• Priority Level: X > H > L
• For equal priority levels, vector with lowest address takes precedence.
(15) Subroutine stack levels
- A maximum of 1536 levels (set stack inside RAM)
(16) Multiplication and division
- 16 bits × 8 bits (5 instruction-cycle times)
- 24 bits × 16 bits (12 instruction-cycle times)
- 16 bits ÷ 8 bits (8 instruction-cycle times)
- 24 bits ÷ 16 bits (12 instruction-cycle times)
(17) Oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- CF oscillation circuit used for the system clock
- Crystal oscillation circuit used for the system clock
- Built-in frequency variable RC oscillation circuit used for the system clock
(17) System clock divider
- operable on the lowest power consumption
- Minimum instruction cycle time (300ns, 600ns, 1.2µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be
switched by program (when using 10MHz main clock)
Ver.1.00
3/27
LC875780A/72A
(18) Standby function
- HALT mode
The HALT mode stops program execution while the peripheral circuits keep operating and
minimizes power consumption. This operation mode can be released by a system reset or an
interrupt request.
- HOLD mode
The HOLD mode stops program execution and all oscillation circuits: CF, RC and Crystal
oscillations. This mode can be released by the following conditions.
1. Supply "L" level to the reset terminal (
RES
)
2. Supply the selected level to at lease one of INT0, INT1, INT2, INT4 INT5.
3. Supply an interrupt condition to Port 0.
- X’tal HOLD mode
The X’tal HOLD mode stops program execution and all peripheral circuits except for the base timer.
The crystal oscillator maintains its state at HOLD mode inception. This mode can be released by
the following conditions.
1. Supply "L" level to the reset terminal (
RES
).
2. Supply the selected level to at least one of INT0, INT1, INT2, INT4, INT5
3. Supply an interrupt condition to Port 0.
4. Supply an interrupt condition to the base timer circuit.
(19) Shipping form
- QIP64E
- SQFP64
(20) Development tools
- Evaluation (EVA) chip
: LC876093
- Emulator
: EVA62S + ECB876600A + SUB875700 + POD64QFP or POD64SQFP
- Flash ROM version : LC87F57C8A
4/27
Ver.1.00
LC875780A/72A
Pin Assignment
PA2/CS0#
PA3/WR#
PA4/RD#
PA5/RS
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
PC6/A6
PC7/A7
PB0/D0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P73/INT3/T0IN
RES#
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P10/SO0
P11/SI0/SB0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
P12/SCK0
2
P13/SO1
3
P14/SI1/SB1
4
P15/SCK1
5
P16/T1PWML
6
P17/T1PWMH/BUZ
7
PWM1
8
PWM0
9
VDD2
10 11 12 13 14 15 16
P00
P01
VSS2
P02
P03/AN3
P04/AN4
P05/AN5
32
31
30
29
28
27
PB2/D2
PB3/D3
PB4/D4
PB5/D5
PB6/D6
PB7/D7
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN
P23/INT4/T1IN
P22/INT4/T1IN
P21/INT4/T1IN
P20/INT4/T1IN
P07/AN7
P06/AN6
PB1/D1
26
25
24
23
22
21
20
19
18
17
VDD3
LC875700A
QIP64E
SQFP64
Ver.1.00
VSS3
5/27
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