Ordering number : ENN7972
LC875BP4A
LC875BM2A
LC875BJ0A
LC875BH4A
Overview
CMOS IC
ROM 256K/224K/192K/176K byte, RAM 4096K byte on-chip
8-bit 1-chip Microcontroller
The LC875BP4A, LC875BM2A, LC875BJ0A, LC875BH4A is 8-bit single chip microcontroller with the following one-
chip features :
•
CPU : Operable at a minimum bus cycle time of 100ns
•
On-chip ROM Capacity : LC875BP4A 256K bytes
: LC875BM2A 224K bytes
: LC875BJ0A 192K bytes
: LC875BH4A 176K bytes
•
On-chip RAM Capacity : 4K bytes
•
Two high performance 16-bit timer/counters (can be divided into 8-bit timers)
•
Four 8-bit timers with prescalers
•
Timer for use as date/time clock
•
Two synchronous serial I/O ports (with automatic block transmit/receive function)
•
One asynchronous/synchronous serial I/O port
•
Two UART ports (full duplex)
•
12-bit PWM × 4
•
12-channel × 8-bit AD converter
•
High speed clock counter
•
System clock divider
•
27-source 10-vectored interrupt system
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.00
92706 / 81205HKIM B8-7735 No.7972-1/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Features
Read Only Memory (ROM)
•
262144 × 8-bits (LC875BP4A)
•
229376 × 8-bits (LC875BM2A)
•
196608 × 8-bits (LC875BJ0A)
•
180224 × 8-bits (LC875BH4A)
Random Access Memory (RAM) : 4096 × 9-bit
Bus Cycle Time
•
100ns (10MHz)
Note : Bus cycle time indicates the speed to read ROM.
Minimum Instruction Cycle Time (tCYC)
•
300ns (10MHz)
Ports
•
Input/output ports
Input/output programmable for each bit individually
Data direction programmable in two bits
Data direction programmable in nibble units
•
Input ports
•
Oscillator pins
•
Reset pin
•
Power supply
64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn, S2Pn,
PWM0, PWM1, XT2)
16 (PEn, PFn)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
8 (VSS1 to 4, VDD1 to 4)
Timer
•
Timer 0 : 16-bit timer/counter with capture register
Mode 0 :8-bit timer with 8-bit programmable prescaler (with an 8-bit capture register) × 2-channels
Mode 1 :8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with 8-bit capture register)
Mode 2 :16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3 :16-bit counter (with a 16-bit capture register)
•
Timer 1 : 16-bit timer/counter that support PWM/ toggle output
Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter
(with toggle outputs )
Mode 1 : 8-bit PWM with an 8-bit prescaler × 2-channels
Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(Toggle outputs also present at the lower-order 8-bits)
Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8-bits can be used as PWM.)
•
Timer 4 : 8-bit timer with a 6-bit prescaler
•
Timer 5 : 8-bit timer with a 6-bit prescaler
•
Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1. The clock is selectable from sub-clock (32.768kHz crystal oscillation), system clock or programmable
prescaler output of timer 0.
2. Interrupt are programmablein 5 different time schemes.
High Speed Clock Counter
1. Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2. Can generate output real time.
No.7972-2/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Serial Interface
•
SIO 0 : 8-bit synchronous serial interface
1. LSB first/MSB first-function available
2. An internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)
3. Consecutive automatic data communication (1 to 256-bits)
•
SIO 1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1 : Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud-rate 8 to 2048 tCYC)
Mode 2 : Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection)
•
SIO2 : 8-bit synchronous serial interface
1. LSB-first
2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)
3. Consecutive automatic data communication (1 to 32 bytes)
UART :2-channels
1. Full duplex
2. 7/8/9 bit data bits selectable
3. 1stop bit
4. built-in baudrate generator
AD Converter
•
12-channel × 8-bit AD converter
PWM
•
4-channel × synchronous variable 12-bit PWM
Remote Receiver Circuit (share with P73/INT3/T0IN terminal)
•
Noise rejection function (The filtering time of the noise rejection filter (1tCYC/32 tCYC/128 tCYC) can be switched
by program.)
Watchdog Ttimer
•
External RC circuit is required.
•
Interrupt or system reset is activated when the timer overflows.
Interrupts
•
27-source and 10-vectored interrupt function :
1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level nesting possible.
During interrupt handling, an equal or lower level interrupt request is refused.
2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes
precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Selectable Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/INT5/base timer
T0H
T1L/T1H
SIO0/UART1, 2 receive
SIO1/SIO2/UART1, 2 transmit
ADC/T6/T7/PWM4, PWM5
Port 0/T4/T5/PWM0, PWM1
Interrupt Signal
• Priority Level : X > H > L
• For equal priority levels, vector with lowest address takes precedence.
No.7972-3/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Subroutine Stack Levels
•
A maximum of 3072 levels (set stack inside RAM)
Multiplication and division
•
16-bits × 8-bits (5 instruction-cycle times)
•
24-bits × 16-bits (12 instruction-cycle times)
•
16-bits ÷ 8-bits (8 instruction-cycle times)
•
24-bits ÷ 16-bits (12 instruction-cycle times)
Oscillation Circuits
•
Built-in RC oscillation circuit used for the system clock
•
CF oscillation circuit used for the system clock
•
Crystal oscillation circuit used for the system clock
System Clock Divider
•
Operable on the lowest power consumption
•
Minimum instruction cycle time (300ns, 600ns, 1.2µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched by
program (when using 10MHz main clock)
Standby Function
•
HALT mode
The HALT mode stops program execution while the peripheral circuits keep operating and minimizes power
consumption. This operation mode can be released by a system reset or an interrupt request.
•
HOLD mode
The HOLD mode stops program execution and all oscillation circuits : CF, RC and Crystal oscillations.
This mode can be released by the following conditions.
1. Supply "L" level to the reset terminal (RES)
2. Supply the selected level to at lease one of INT0, INT1, INT2, INT4, INT5.
3. Supply an interrupt condition to Port 0.
•
X’tal HOLD mode
The X’tal HOLD mode stops program execution and all peripheral circuits except for the base timer. The crystal
oscillator maintains its state at HOLD mode inception. This mode can be released by the following conditions.
1. Supply "L" level to the reset terminal (RES).
2. Supply the selected level to at least one of INT0, INT1, INT2, INT4, INT5.
3. Supply an interrupt condition to Port 0.
4. Supply an interrupt condition to the base timer circuit.
Shipping Form
•
QFP100E (Lead Free Product)
•
TQFP100 (Lead Free Product)
Development Tools
•
Evaluation (EVA) chip : LC87EV690
•
Emulator
: EVA62S + ECB876600D + SUB875200 + POD100QFP or POD100SQFP Type B
: ICE-B877300 + SUB875200 + POD100QFP or POD100SQFP Type B
No.7972-4/25
LC875BP4A/875BM2A/875BJ0A/875BH4A
Package Dimensions
unit : mm
3151A
Package Dimensions
unit : mm
3274
No.7972-5/25
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