Integrated
Circuit
Systems, Inc.
ICS9179B-01
Low Skew Buffers
General Description
The
ICS9179B-01
generates SDRAM clock buffers
required for high speed RISC or CISC microprocessor
systems such as Intel PentiumPro or Pentium II. An
output enable is provided for testability.
The device is a buffer with low output to output skew. This
is a Fanout buffer device, not using an internal PLL. This
buffer can also be a feedback to an external PLL stage for
phase synchronization to a master clock.
The individual clock outputs are addressable through I
2
C
to be enabled, or stopped in a low state for reduced EMI
when the lines are not needed.
Features
•
•
•
•
•
•
•
High speed, low noise non-inverting (0:17) buffer for
SDRAM clock buffer applications.
Supports up to four SDRAM DIMMS
Synchronous clocks skew matched to 250 ps
window on SDRAM.
I
2
C Serial Configuration interface to allow individual
clocks to be stopped.
Multiple VDD, VSS pins for noise reduction
Tri-state pin for testing
Custom configurations available
3.0V – 3.7V supply range
48-pin SSOP package
•
•
Block Diagram
Pin Configuration
48-Pin SSOP
0256D—05/02/02
PentiumPro is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
ICS9179B-01
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE DESCRIPTION
4, 5, 8, 9
SDRAM (0:3)
O U T SDRAM Byte 0 clock outputs
1
13, 14, 17, 18
SDRAM (4:7)
O U T SDRAM Byte 1 clock outputs
1
31, 32, 35, 36 SDRAM (8:11) O U T SDRAM Byte 2 clock outputs
1
40, 41, 44, 45 SDRAM (12:15) O U T SDRAM Byte 3 clock outputs
1
21, 28
SDRAM (16:17) O U T SDRAM clock outputs useable for feedback.
1
11
BU F _ I N
I N Input for buffers
T - tat
38
OE
I N pr illsup.es all outputs when held LOW. Has inter nal
u -
2
24
SDATA
I / O Data pin for I
2
C circuitr y
3
25
SCLK
I / O Clock pin for I
2
C circuitr y
3
3, 7, 12, 16,
20, 29, 33, 37,
VDD
P W R 3.3V Power supply for SDRAM buffer
42, 46
6, 10, 15, 19,
22, 27, 30, 34,
GND
P W R Ground for SDRAM buffer
39, 43
23
VDDS
P W R 3.3V Power supply for I
2
C circuitr y
26
GNDS
P W R Ground for I
2
C circuitr y
1, 2, 47, 48
N/C
-
Pins are not inter nally connected
Notes:
1.
At power up all eighteen SDRAM outputs are enabled and active.
2.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
3.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well
for complete platform flexibility.
Power Groups
VDD = Power supply for SDRAM buffer
VDDS = Power supply for I
2
C circuitry
Ground Groups
GND = Ground for SDRAM buffer
GNDS = Ground for I
2
C circuitry
2
ICS9179B-01
Technical Pin Function Descriptions
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for
SDRAM(0:17).
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from
Ground to this level. For the actual guaranteed high and
low voltage levels for the Clocks, please consult the DC
parameter table in this data sheet.
GND
This is the power supply ground (common or negative)
return pin for the internal core logic and all the output
buffers.
SDRAM(0:17)
These Output Clocks are use to drive Dynamic RAM’s
and are low skew copies of the CPU Clocks. The voltage
swing of the SDRAM’s output is controlled by the supply
voltage that is applied to VDD of the device, operates at
3.3 volts.
I
2
C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in
the I
2
C protocol. It will allow read-back of the registers.
See configuration map for register functions. The I
2
C
specification in Philips I
2
C Peripherals Data Handbook
(1996) should be followed.
BUF_IN
Input for Fanout buffers (SDRAM 0:17).
OE
OE tristates all outputs when held low.
VDDS
This is the power supply to I
2
C circuitry.
GNDS
This is the ground to I
2
C circuitry.
3
ICS9179B-01
General I
2
C serial interface information
A.
For the clock generator to be addressed by an I
2
C controller, the following address must be sent as a start
sequence, with an acknowledge bit between each byte.
Clock Generator
Address (7 bits)
A(6:0) & R/W# ACK
D2
(H)
B.
+ 8 bits
dummy
command
code
ACK
+ 8 bits
dummy Byte
count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
The clock generator is a slave/receiver I
2
C component. It can "read back "(in Philips I
2
C protocol) the data stored
in the latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet
the Intel SMB PIIX4 protocol.
Clock Generator
Address (7 bits)
A(6:0) & R/W# ACK
D3
(H)
C.
D.
E.
F.
Byte 0
ACK
Byte 1
ACK
Byte 0, 1, 2, etc in sequence until STOP.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only block writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
At power-on, all registers are set to a default condition. Bytes 0 through 2 default to a 1 (Enabled output state).
G.
H.
Serial Configuration Command Bitmaps
Byte 0: SDRAM Clock Register
BIT
Bit7
PIN#
18
PWD
DESCRIPTION
1
SDRAM7
(Act/Inact)
1
SDRAM6
(Act/Inact)
1
SDRAM5
(Act/Inact)
1
SDRAM4
(Act/Inact)
1
SDRAM3
(Act/Inact)
1
SDRAM2
(Act/Inact)
1
SDRAM1
(Act/Inact)
1
SDRAM0
(Act/Inact)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
17
14
13
9
8
5
4
Notes:
1 = Enabled; 0 = Disabled, outputs held low
Note:
PWD = Power-Up Default
4
ICS9179B-01
Functionality
OE#
0
1
SDRAM (0:3)
Hi-Z
1 X BUF_IN
SDRAM (4:7)
Hi-Z
1 X BUF_IN
SDRAM (8:11)
Hi-Z
1 X BUF_IN
SDRAM
(12:15)
Hi-Z
1 X BUF_IN
SDRAM
(16:17)
Hi-Z
1 X BUF_IN
Byte 1: SDRAM Clock Register
BIT
PIN#
PWD
Byte 2: PCICLK Clock Register
BIT
PIN# PWD
DESCRIPTION
SDRAM17
(Act/Inact)
SDRAM16
(Act/Inact)
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
45
44
41
40
36
35
32
31
1
1
1
1
1
1
1
1
DESCRIPTION
SDRAM15
(Act/Inact)
SDRAM14
(Act/Inact)
SDRAM13
(Act/Inact)
SDRAM12
(Act/Inact)
SDRAM11
(Act/Inact))
SDRAM10
(Act/Inact)
SDRAM9
(Act/Inact)
SDRAM8
(Act/Inact))
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
28
21
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Notes:
1 = Enabled; 0 = Disabled, outputs held low
Notes:
1 = Enabled; 0 = Disabled, outputs held low
Note:
PWD = Power-Up Default
ICS9179B-01 Power Management
The values below are estimates of target specifications.
Condition
No Clock Mode
(BUF_IN - VDD1 or
GND)
I
2
C Circuitry Active
Active 66MHz
(BUF_IN = 66.66MHz)
Active 100MHz
(BUF_IN = 100.00MHz)
Max 3.3V supply consumption
Max discrete cap loads
VDD = 3.465V
All static inputs = VDD or GND
3mA
115mA
180mA
5
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