INTEGRATED CIRCUITS
74ALVC16835
18-bit universal bus driver with
5V tolerant inputs (3-State)
Product specification
IC24 Data Handbook
1999 Mar 18
Philips
Semiconductors
Philips Semiconductors
Product specification
18-bit universal bus driver with 5V tolerant inputs
(3-State)
74ALVC16835
FEATURES
•
Wide supply voltage range of 1.2V to 3.6V
•
Complies with JEDEC standard no. 8-1A.
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Current drive
±
24 mA at 3.0 V
•
MULTIBYTE
TM
flow-through standard pin-out architecture
•
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
PIN CONFIGURATION
NC
NC
Y
0
GND
Y
1
Y
2
V
CC
Y
3
Y
4
Y
5
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A
0
GND
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
CP
GND
•
Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74ALVC16835 is a 18–bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
When LE is HIGH, the A to Y data flow is transparent. When LE is
LOW and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A–data is stored in the
latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF–state. Operation of the OE
input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
GND
Y
12
Y
13
Y
14
V
CC
Y
15
Y
16
GND
Y
17
OE
LE
SH00130
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
≤
2.5ns
PARAMETER
SYMBOL
Propagation delay
An to Yn;
t
PHL
/t
PLH
LE to Yn;
CP to Yn
F
max
C
I
C
I/O
Maximum clock frequency
Input capacitance
Input/Output capacitance
CONDITIONS
V
CC
= 3.3V, C
L
= 50pF
V
CC
= 3.3V, C
L
= 50pF
TYPICAL
2.3
2.6
2.5
350
4.0
8.0
transparent mode
Output enabled
Output disabled
Clocked mode
Output enabled
Output disabled
13
3
22
15
UNIT
ns
MHz
pF
pF
C
PD
Power dissipation capacitance per buffer
dissi ation ca acitance er
V
I
= GND to V
CC1
pF
F
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
1999 Mar 18
2
853-2095 21052
Philips Semiconductors
Product specification
18-bit universal bus driver with 5V tolerant inputs
(3-State)
74ALVC16835
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
TEMPERATURE
RANGE
–40°C to +85°C
OUTSIDE NORTH
AMERICA
74ALVC16835 DGG
NORTH AMERICA
AC16835 DGG
DRAWING
NUMBER
SOT364-1
PIN DESCRIPTION
PIN NUMBER
1, 2, 55
3, 5, 6, 8, 9, 10, 12, 13,
14, 15, 16, 17, 19, 20,
21, 23, 24, 26
4, 11, 18, 25, 32, 39, 46,
53, 56
7, 22, 35, 50
27
28
30
54, 52, 51, 49, 48, 47,
45, 44, 43, 42, 41, 40,
38, 37, 36, 34, 33, 31
SYMBOL
NC
Y
0
to Y
17
NAME AND FUNCTION
No connection
Data outputs
LOGIC SYMBOL (IEEE/IEC)
OE
CP
LE
27
30
28
C3
G2
EN1
2C3
GND
V
CC
OE
LE
CP
A
0
to A
17
Ground (0V)
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active HIGH)
Clock input
Data inputs
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
1
∇
1
3D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
LOGIC SYMBOL
Y
12
Y
13
Y
14
OE
Y
15
Y
16
CP
Y
17
SH00154
LE
A
0
FUNCTION TABLE
D
LE
CP
Y
0
INPUTS
OE
H
L
L
L
L
SH00138
LE
X
H
H
L
L
L
L
CP
X
X
X
↑
↑
H
L
A
X
L
H
L
H
X
X
OUTPUTS
Z
L
H
L
H
Y
01
Y
02
TO THE 17 OTHER CHANNELS
L
L
H
L
X
Z
↑
=
=
=
=
=
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
1999 Mar 18
3
Philips Semiconductors
Product specification
18-bit universal bus driver with 5V tolerant inputs
(3-State)
74ALVC16835
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
DC supply voltage (for low-voltage applications)
V
I
V
O
T
amb
t
r
, t
f
DC Input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
CONDITIONS
MIN
2.3
3.0
1.2
0
0
–40
0
0
MAX
2.7
3.6
3.6
V
CC
V
CC
+85
20
10
V
V
°C
ns/V
V
UNIT
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC in ut voltage
input
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic medium-shrink (SSOP)
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55°C derate linearly with 11.3 mW/K
above +55°C derate linearly with 8 mW/K
V
I
t0
For control pins
1
For data inputs
1
V
O
uV
CC
or V
O
t
0
Note 1
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +4.6
–0.5 to V
CC
+0.5
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
850
600
V
mA
V
mA
mA
°C
mW
UNIT
V
mA
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1999 Mar 18
4
Philips Semiconductors
Product specification
18-bit universal bus driver with 5V tolerant inputs
(3-State)
74ALVC16835
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IH
HIGH level Input voltage
V
CC
= 2.3 to 2.7V
V
CC
= 2.7 to 3.6V
LOW level Input voltage
V
CC
= 2.3 to 2.7V
V
CC
= 2.7 to 3.6V
V
CC
= 2 3 to 3 6V; V
I
= V
IH
or V
IL
; I
O
= –100µA
100µA
2.3 3.6V;
V
CC
= 2.3V; V
I
= V
IH
or V
IL
; I
O
= –6mA
V
O
OH
HIGH level output voltage
V
CC
= 2.3V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
= 2 3 to 3 6V; V
I
= V
IH
or V
IL
; I
O
= 100µA
2.3 3.6V;
V
CC
= 2.3V; V
I
= V
IH
or V
IL
; I
O
= 6mA
V
OL
LOW level output voltage
V
CC
= 2.3V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
I
I
I
OZ
I
CC
∆I
CC
Input leakage current
g
3-State output OFF-state current
Quiescent supply current
Additional quiescent supply current
V
CC
= 2 3 to 3 6V;
2.3 3.6V;
V
I
= V
CC
or GND
V
CC
= 2.3 to 3.6V; V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND
V
CC
= 2.3 to 3.6V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 2.3V to 3.6V; V
I
= V
CC
– 0.6V; I
O
= 0
V
CC
*0.2
02
V
CC*
0.3
V
CC*
0.6
V
CC*
0.5
V
CC*
0.6
V
CC
*1.0
1.7
2.0
TYP
1
1.2
V
1.5
1.2
1.5
V
CC
V
CC*
0.08
V
CC*
0.26
V
CC*
0.14
V
CC*
0.09
V
CC*
0.28
GND
0.07
0.15
0.14
0.27
0.1
0.1
0.2
150
0.20
0 20
0.40
0.70
0.40
0.55
5
10
40
750
µ
µA
µA
µA
µA
V
V
V
V
0.7
V
0.8
MAX
UNIT
V
IL
NOTES:
1. All typical values are at T
amb
= 25°C.
1999 Mar 18
5
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