TECHNOLOGY, INC.
2 MEG x 8
FPM DRAM
MT4C2M8B1
MT4LC2M8B1
DRAM
FEATURES
• JEDEC- and industry-standard x8 pinouts, timing,
functions and packages
• High-performance, low power CMOS silicon-gate
process
• Single power supply (+3.3V
±0.3V
or 5V
±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• Optional Self Refresh (S) for low power data retention
• 2,048-cycle refresh (11 row, 10 column addresses)
• 5V-tolerant inputs and I/Os on 3.3V devices
PIN ASSIGNMENT (Top View)
28-Pin SOJ
(DA-3)
V
CC
DQ1
DQ2
DQ3
DQ4
WE#
RAS#
NC
A10
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
DQ8
DQ7
DQ6
DQ5
CAS#
OE#
A9
A8
A7
A6
A5
A4
Vss
V
CC
DQ1
DQ2
DQ3
DQ4
WE#
RAS#
NC
A10
A0
A1
A2
A3
Vcc
28-Pin SOJ
(DA-4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
DQ8
DQ7
DQ6
DQ5
CAS#
OE#
A9
A8
A7
A6
A5
A4
Vss
OPTIONS
• Voltage
3.3V
5V
• Packages
Plastic 28-pin SOJ (300 mil)
Plastic 28-pin SOJ (400 mil)
Plastic 28-pin TSOP (300 mil)
• Timing
60ns access
• Refresh Rate
Standard Refresh (32ms period)
Self Refresh (128ms period)
MARKING
LC
C
DJ
DW
TG
-6
None
S
28-Pin TSOP
(DB-3 )
V
CC
DQ1
DQ2
DQ3
DQ4
WE#
RAS#
NC
A10
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
DQ8
DQ7
DQ6
DQ5
CAS#
OE#
A9
A8
A7
A6
A5
A4
Vss
• Part Number Example: MT4LC2M8B1DJ-6
Note: The 2 Meg x 8 FPM DRAM base number differentiates the offerings in
one place -
MT4LC2M8B1.
The third field distinguishes the low voltage
offering: LC designates Vcc = 3.3V and C designates Vcc = 5V.
Note:
The # symbol indicates signal is active LOW.
KEY TIMING PARAMETERS
SPEED
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
2 MEG x 8 FPM DRAM PART NUMBERS
PART NUMBER
MT4LC2M8B1DJ
MT4LC2M8B1DJS
MT4LC2M8B1TG
MT4LC2M8B1TGS
MT4C2M8B1DJ
MT4C2M8B1DJS
MT4C2M8B1TG
MT4C2M8B1TGS
V
CC
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
110ns
60ns
35ns
30ns
15ns
40ns
2 Meg x 8 FPM DRAM
D50.pm5 – Rev. 3/97
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
2 MEG x 8
FPM DRAM
GENERAL DESCRIPTION
The 2 Meg x 8 DRAM is a randomly accessed, solid-
state memory containing 16,777,216 bits organized in a
x8 configuration. Each byte is uniquely addressed
through the 21 address bits during READ or WRITE
cycles. The address is entered first by RAS# latching 11
bits (A0-A10) and then CAS# latching 10 bits (A0-A9).
The CAS# control also determines whether the cycle will
be a refresh cycle (RAS#-ONLY) or an active cycle (READ,
WRITE or READ WRITE) once RAS# goes LOW.
READ or WRITE cycles are selected by WE#. A logic
HIGH on WE# dictates READ mode while a logic LOW on
WE# dictates WRITE mode. During a WRITE cycle, data-in
(D) is latched by the falling edge of WE# or CAS#, which-
ever occurs last. Taking WE# LOW will initiate a WRITE
cycle, selecting DQ1 through DQ8. If WE# goes LOW prior
to CAS# going LOW, the output pin(s) remain open
(High- Z) until the next CAS# cycle. If WE# goes LOW after
CAS# goes LOW and data reaches the output pins, data-out
(Q) is activated and retains the selected cell data as long as
CAS# and OE# remain LOW (regardless of WE# or RAS#).
This late WE# pulse results in a READ WRITE cycle.
The eight data inputs and eight data outputs are routed
through eight pins using common I/O, and pin direction is
controlled by OE# and WE#.
or HIDDEN) so that all 2,048 combinations of RAS# ad-
dresses (A0 -A10) are executed at least every 32ms, regard-
less of sequence. The CBR REFRESH cycle will also invoke
the refresh counter and controller for row-address control.
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR, or HIDDEN) so that all
2,048 combinations of RAS# addresses are executed within
t
REF (MAX), regardless of sequence. The CBR and SELF
REFRESH cycles will invoke the internal refresh counter for
automatic RAS# addressing.
An optional SELF REFRESH mode is also available on the
S version. The “S” option allows the user the choice of a fully
static low-power data retention mode, or a dynamic refresh
mode at the extended refresh period of 128ms. The optional
SELF REFRESH feature is initiated by performing a CBR
REFRESH cycle and holding RAS# LOW for the specified
t
RASS. Additionally, the “S” option allows for an extended
refresh period of 128ms, or 62.5µs per row if using distrib-
uted CBR REFRESH. This refresh rate can be applied during
normal operation, as well as during a standby or BATTERY
BACKUP mode.
The SELF REFRESH mode is terminated by driving
RAS# HIGH for a minimum time of
t
RPS. This delay allows
for the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH tran-
sition. If the DRAM controller uses a distributed refresh
sequence, a burst refresh is not required upon exiting SELF
REFRESH. However, if the DRAM controller utilizes RAS#-
ONLY or burst refresh sequence, all 2,048 rows must be
refreshed within the average internal refresh rate prior to
the resumption of normal operation.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (A0 -A10) page boundary. The FAST
PAGE MODE cycle is always initiated with a row address
strobed-in by RAS# followed by a column address strobed-
in by CAS#. CAS# may be toggled-in by holding RAS#
LOW and strobing-in different column addresses, thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST PAGE MODE operation.
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is also preconditioned for the next cycle during the
RAS# HIGH time. Memory cell data is retained in its correct
state by maintaining power and executing any RAS# cycle
(READ, WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR,
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
2 Meg x 8 FPM DRAM
D50.pm5 – Rev. 3/97
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
2 MEG x 8
FPM DRAM
FUNCTIONAL BLOCK DIAGRAM
WE#
DATA-IN BUFFER
CAS#
8
NO. 2 CLOCK
GENERATOR
DQ8
DATA-OUT
BUFFER
OE#
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLLER
10
DQ1
COLUMN
DECODER
8
1024
8
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
11
ROW
ADDRESS
BUFFERS (11)
1024 x 8
ROW
DECODER
11
11
2048
2048 x 1024 x 8
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
V
CC
V
SS
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
READ
EARLY WRITE
READ WRITE
FAST-PAGE-MODE
READ
FAST-PAGE-MODE
WRITE
FAST-PAGE-MODE
READ-WRITE
HIDDEN
REFRESH
CBR REFRESH
SELF REFRESH
2 Meg x 8 FPM DRAM
D50.pm5 – Rev. 3/97
RAS#
H
L
L
L
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
READ
WRITE
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
H→L
CAS#
H→X
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L
L
H
L
L
WE#
X
H
L
H→L
H
H
L
L
H→L
H→L
H
L
X
H
H
OE#
X
L
X
L→H
L
L
X
X
L→H
L→H
L
X
X
X
X
t
R
t
C
DQs
High-Z
Data-Out
Data-In
Data-Out, Data-In
Data-Out
Data-Out
Data-In
Data-In
Data-Out, Data-In
Data-Out, Data-In
Data-Out
Data-In
High-Z
High-Z
High-Z
X
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
ROW
ROW
X
X
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
X
X
RAS#-ONLY REFRESH
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
2 MEG x 8
FPM DRAM
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
pin Relative to V
SS
:
3.3V ................................................................ -1V to +4.6V
5V ...................................................................... -1V to +7V
Voltage on NC, Inputs or I/O pins Relative to V
SS
:
3.3V ................................................................ -1V to +5.5V
5V ...................................................................... -1V to +7V
Operating Temperature, T
A
(ambient) .......... 0°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 2, 3)
3.3V
PARAMETER/CONDITION
Supply Voltage
Input High Voltage:
Valid Logic 1; all inputs, I/Os and any NC
Input Low Voltage:
Valid Logic 0; all inputs, I/Os and any NC
Input Leakage Current:
Any input at V
IN
(0V
≤
V
IN
≤
V
IH
MAX
);
all other pins not under test = 0V
Output High Voltage:
I
OUT
= -2mA (3.3V), -5mA (5V)
Output Low Voltage:
I
OUT
= 2mA (3.3V), 4.2mA (5V)
Output Leakage Current:
Any output at V
OUT
(0V
≤
V
OUT
≤
5.5V);
DQ is disabled and in High-Z state
SYMBOL
V
CC
V
IH
V
IL
I
I
MIN
3.0
2.0
-1.0
-2
MAX
3.6
5.5
0.8
2
MIN
4.5
2.4
-1.0
-2
5V
MAX
5.5
V
CC
+1
0.8
2
UNITS
V
V
V
µA
NOTES
V
OH
V
OL
I
OZ
2.4
-
-5
-
0.4
5
2.4
-
-5
-
0.4
5
V
V
µA
2 Meg x 8 FPM DRAM
D50.pm5 – Rev. 3/97
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
2 MEG x 8
FPM DRAM
I
CC
OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3) (V
CC
MIN
≤
V
CC
≤
V
CC
MAX
)
PARAMETER/CONDITION
STANDBY CURRENT: TTL
(RAS# = CAS# = V
IH
)
STANDBY CURRENT: CMOS (non-S version only)
(RAS# = CAS# = other inputs = V
CC
-0.2V)
STANDBY CURRENT: CMOS (S version only)
(RAS# = CAS# = other inputs = V
CC
-0.2V)
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
REFRESH CURRENT: Extended (S version only)
Average power supply current: CAS# = 0.2V or CBR cycling;
RAS# =
t
RAS (MIN); WE# = V
CC
-0.2V; A0-A11, OE# and
D
IN
= V
CC
-0.2V or 0.2V (D
IN
may be left open),
t
RC = 31.25µs
REFRESH CURRENT: Self (S version only)
Average power supply current: CBR with RAS#
≥
t
RASS (MIN) and
CAS# held LOW; WE# = V
CC
-0.2V; A0-A11,
OE# and D
IN
= V
CC
-0.2V or 0.2V (D
IN
may be left open)
SYM
I
CC
1
I
CC
2
I
CC
2
SPEED
-6
-6
-6
3.3V
1
500
150
5V
2
500
150
UNITS
mA
µA
µA
NOTES
I
CC
3
-6
100
130
mA
3, 22
I
CC
4
-6
80
100
mA
3, 22
I
CC
5
-6
100
130
mA
3, 22
I
CC
6
-6
100
130
mA
3, 4
I
CC
7
-6
300
300
µA
3, 4
I
CC
8
-6
300
300
µA
2 Meg x 8 FPM DRAM
D50.pm5 – Rev. 3/97
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
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