address inputs, A(12:0); and eight bidirectional data lines,
DQ(7:0). E1 and E2 are device enable inputs that control device
selection, active, and standby modes. Asserting both E1 and E2
enables the device, causes I
DD
to rise to its active value, and
decodes the 13 address inputs to select one of 8,192 words in
the memory. W controls read and write operations. During a
read cycle, G must be asserted to enable the outputs.
2
WRITE CYCLE
A combination of W less than V
IL
(max), E1 less than V
IL
(max),
and E2 greater than V
IH
(min) defines a write cycle. The state of
G is a “don’t care” for a write cycle. The outputs are placed in
the high-impedance state when either G is greater than
V
IH
(min), or when W is less than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access shown in
figure 4a, is defined by a write terminated byW going high, with
E1 and E2 still active. The write pulse width is defined by t
WLWH
when the write is initiated by W, and by t
ETWH
when the write
is initiated by the latter of E1 or E2. Unless the outputs have
been previously placed in the high-impedance state by G, the
user must wait t
WLQZ
before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in
figure 4b, is defined by a write terminated by the latter of E1 or
E2 going inactive. The write pulse width is defined by t
WLEF
when the write is initiated by W, and by t
ETEF
when the write
is initiated by the latter of E1 or E2 going active. For the W
initiated write, unless the outputs have been previously placed
in the high-impedance state by G, the user must wait t
WLQZ
before applying data to the eight bidirectional pins DQ(7:0) to
avoid bus contention.
Total Dose
Table 2. Radiation Hardness
Design Specifications
1
1.0E6
1.0E9
1.0E12
1.0E-10
3.0E14
rads(Si)
rads(Si)/s 20ns pulse
rads(Si)/s 20ns pulse
errors/bit day
2
n/cm
2
Dose Rate Upset
Dose Rate Survival
Single-Event Upset
Neutron Fluencs
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% Adam’s worst case spectrum (-55
o
C to 125+
o
C).
Table 3. SEU versus Temperature
10
-4
10
-6
SEU
errors/bit-day
10
-8
10
-10
10
-12
10
-13
10
-14
10
-16
10
-13
10
-11
10
-10
RADIATION HARDNESS
The UT67164 SRAM incorporates special design and layout
features which allow operation in high-level radiation
environments.
-55
-35
-15
5
25
45
65
85
105 125
Temperature (
o
C)
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
LU
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
Thermal resistance, junction-to-case
2
Latchup immunity
DC input current
LIMITS
-0.5 to 7.0V
-0.5 to V
DD
+ 0.5
-65 to +150°C
1.0W
+150°C
10°C/W
+/-150mA
+/-
10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
4.5 to 5.5V
-55 to +125°C
0V to V
DD
UNITS
V
o
C
V
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(V
DD
= 5.0V±10%; -55°C <Tc < +125°C)
SYMBOL
V
IH
V
IL
V
OL
V
OH
C
IN 1
C
IO 1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
I
OL
= +/- 4.0mA, V
DD
= 4.5V
I
OH
= +/-4mA, V
DD
= 4.5V
ƒ
= 1MHz @ 0V, V
DD
= 4.5V
ƒ
= 1MHz @ 0V, V
DD
= 4.5V
V
IN
= V
DD
and V
SS
V
O
= V
DD
and V
SS
V
DD
= 5.5V
G = 5.5V
I
OS 2, 3
Short-circuit output current
V
DD
= 5.5V, V
O
= V
DD
V
DD
= 5.5V, V
O
= 0V
I
DD
(OP)
I
DD
(SB)
pre-rad
I
DD
(SB)
post-rad
Supply current operating @1MHz
CMOS inputs (I
OUT
= 0)
V
DD
= 5.5V
Supply current standby
CMOS inputs (I
OUT
= 0)
E1 = V
DD
- 0.5, V
DD
= 5.5V
CMOS inputs (I
OUT
= 0)
CS1 = negated V
DD
= 5.5V
CS2 = negated
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
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