33LV408
4 Megabit (512K x 8-Bit)
CMOS SRAM
Memory
Logic Diagram
F
EATURES
:
• R
AD
-P
AK
® Technology radiation-hardened against natural
space radiation
• 524,288 x 8 bit organization
· Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effect
· - SEL
TH
: > 68 MeV/mg/cm
2
· - SEU
TH
: = 3 MeV/mg/cm
2
•
- SEU saturated cross section: 6E-9 cm
2
/bit
Package:
- 32-Pin R
AD
-P
AK
® flat packFast access time:
- 20, 25, 30 ns maximum times available
Single 3.3V + 10% power supply
Fully static operation
- No clock or refresh required
Three state outputs
TTL compatible inputs and outputs
Low power:
- Standby: 60 mA (TTL); 10 mA (CMOS)
- Operation: 150 mA (20 ns); 140 mA (25 ns);
130 mA (30 ns)
D
ESCRIPTION
:
DDC's
33LV408 high-density 4 Megabit
SRAM microcircuit features a greater than 100 krad (Si) total
dose tolerance, depending upon space mission. Using
DDC's
radiation-hardened R
AD
-P
AK
® packaging technology, the
33LV408 realizes a high density, high performance, and low
power consumption. Its fully static design eliminates the need
for external clocks, while the CMOS circuitry reduces power
consumption and provides higher reliability. The 33LV408 is
equipped with eight common input/output lines, chip select
and output enable, allowing for greater system flexibility and
eliminating bus contention. The 33LV408 features the same
advanced 512K x 8-bit SRAM, high-speed, and low-power
demand as the commercial counterpart.
DDC's
patented R
AD
-P
AK
® packaging technol-
•
•
•
•
•
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
® provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
08.06.07 REV 3
All data sheets are subject to change without notice
1
(631) 567-5600 - www.ddc-web.com
©2016 Data Device Corporation
All rights reserved.
4 Megabit (512K x 8-Bit) CMOS SRAM
T
ABLE
1. P
INOUT
D
ESCRIPTION
P
IN
12-5, 27, 26, 23, 25, 4,
28, 3, 31, 2, 30, 1
29
22
24
13-15, 17-21
32
16
S
YMBOL
A0-A18
WE
CS
OE
I/O 0-I/O 7
V
CC
V
SS
D
ESCRIPTION
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power
Ground
33LV408
T
ABLE
2. 33LV408 A
BSOLUTE
M
AXIMUM
R
ATINGS
Memory
P
ARAMETER
Voltage on V
CC
supply relative to V
SS
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
S
YMBOL
V
CC
V
IN
, V
OUT
P
D
T
S
T
A
M
IN
-0.5
-0.5
--
-65
-55
M
AX
4.6
V
CC
+0.5
1.0
+150
+125
U
NIT
V
V
W
°
C
°
C
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC
I
SB
I
SB1
V
ARIATION
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
08.06.07 REV 3
All data sheets are subject to change without notice
2
©2016 Data Device Corporation
All rights reserved.
4 Megabit (512K x 8-Bit) CMOS SRAM
T
ABLE
4. 33LV408 R
ECOMMENDED
O
PERATING
C
ONDITIONS
(V
CC
= 3.3 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Supply Voltage
Ground
Input High Voltage
1
Input Low Voltage
2
Thermal Impedance
1. V
IH
(max) = V
CC
+2.0V ac (pulse width < 10 ns) for I < 20 mA
2.
V
IL
(min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA
S
YMBOL
V
CC
V
SS
V
IH
V
IL
M
IN
3.0
0
2.2
-0.3
--
33LV408
M
AX
3.6
0
V
CC
+0.3
0.8
1.21
U
NIT
V
V
V
V
°C/W
Θ
JC
T
ABLE
5. 33LV408 C
APACITANCE
(f = 1.0 MH
Z
, dV = 3.3 V, T
A
= 25
°
C)
P
ARAMETER
Input Capacitance
1
CS1 - CS4,
OE, WE
I/O0-7, I/O8-15, I/O16-23, I/O24-31
Input / Output Capacitance
1
1. Guaranteed by design.
S
YMBOL
C
IN
T
EST
C
ONDITIONS
V
IN
= 0 V
7
28
7
C
OUT
V
I/O
= 0 V
8
pF
M
AX
U
NITS
pF
Memory
T
ABLE
6. 33LV408 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 3.3V + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Current
-20
-25
-30
Standby Power Supply
Current
S
YMBOL
C
ONDITION
I
LI
I
LO
V
OL
V
OH
I
CC
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
,
V
OUT
=V
SS
to V
CC
I
OL
= 8mA
I
OH
= -4mA
Min cycle, 100% Duty, CS=V
IL
, I
OUT
=0mA,
V
IN
= V
IH
or V
IL
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
--
--
--
1, 2, 3
--
150
140
130
60
mA
M
IN
-2
-2
--
2.4
M
AX
2
2
0.4
--
U
NIT
µA
µA
V
V
mA
I
SB
CS = V
IH
, Min Cycle
08.06.07 REV 3
All data sheets are subject to change without notice
3
©
2016 Data Device Corporation
All rights reserved.
4 Megabit (512K x 8-Bit) CMOS SRAM
T
ABLE
6. 33LV408 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 3.3V + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Standby Power Supply
Current - CMOS
Input Capacitance
1
Output Capacitance
1
1. Guaranteed by design.
S
YMBOL
C
ONDITION
I
SB1
C
IN
C
I/O
CS > V
CC
- 0.2V; V
IN
> V
CC
- 0.2V
or V
IN
< 0.2V
V
IN
= 0V, f = 1MHz, T
A
= 25 °C
V
I/O
= 0V
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
M
IN
--
--
--
33LV408
M
AX
10
7
8
U
NIT
mA
pF
pF
T
ABLE
7. 33LV408 AC O
PERATING
C
ONDITIONS AND
C
HARACTERISTICS
(V
CC
= 3.3 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Input Pulse Level
Output Timing Measurement Reference Level
Input Rise/Fall Time
Input Timing Measurement Reference Level
M
IN
0.0
--
--
--
T
YP
--
--
--
--
M
AX
3.0
1.5
3.0
1.5
U
NITS
V
V
ns
V
Memory
T
ABLE
8. 33LV408 AC C
HARACTERISTICS FOR
R
EAD
C
YCLE
(V
CC
= 3.3V + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Read Cycle Time
-20
-25
-30
Address Access Time
-20
-25
-30
Chip Select Access Time
-20
-25
-30
Output Enable to Output Valid
-20
-25
-30
Chip Enable to Output in Low-Z
-20
-25
-30
S
YMBOL
t
RC
S
UBGROUPS
9, 10, 11
20
25
30
t
AA
9, 10, 11
--
--
--
t
CO
9, 10, 11
--
--
--
t
OE
9, 10, 11
--
--
--
t
LZ
9, 10, 11
--
--
--
3
3
3
--
--
--
--
--
--
10
12
14
ns
--
--
--
20
25
30
--
--
--
20
25
30
ns
--
--
--
--
--
--
ns
M
IN
T
YP
M
AX
U
NIT
ns
ns
08.06.07 REV 3
All data sheets are subject to change without notice
4
©2016 Data Device Corporation
All rights reserved.
4 Megabit (512K x 8-Bit) CMOS SRAM
T
ABLE
8. 33LV408 AC C
HARACTERISTICS FOR
R
EAD
C
YCLE
(V
CC
= 3.3V + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Output Enable to Output in Low-Z
-20
-25
-30
Chip Deselect to Output in High-Z
-20
-25
-30
Output Disable to Output in High-Z
-20
-25
-30
Output Hold from Address Change
-20
-25
-30
Chip Select to Power Up Time
-20
-25
-30
Chip Select to Power Down Time
-20
-25
-30
S
YMBOL
t
OLZ
S
UBGROUPS
9, 10, 11
--
--
--
t
HZ
9, 10, 11
--
--
--
t
OHZ
9, 10, 11
--
--
--
t
OH
9, 10, 11
3
5
6
t
PU
9, 10, 11
--
--
--
t
PD
9, 10, 11
--
--
--
10
15
20
--
--
--
0
0
0
--
--
--
--
--
--
--
--
--
5
6
8
--
--
--
5
6
8
--
--
--
0
0
0
--
--
--
M
IN
T
YP
33LV408
M
AX
U
NIT
ns
ns
ns
ns
Memory
ns
ns
T
ABLE
9. 33LV408 F
UNCTIONAL
D
ESCRIPTION
CS
H
L
L
L
1. X = don’t care.
WE
X
1
H
H
L
OE
X
1
H
L
X
1
M
ODE
Not Select
Output Disable
Read
Write
I/O P
IN
High-Z
High-Z
D
OUT
D
IN
S
UPPLY
C
URRENT
I
SB
, I
SB1
I
CC
I
CC
I
CC
08.06.07 REV 3
All data sheets are subject to change without notice
5
©2016 Data Device Corporation
All rights reserved.
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