33LV408RPFE-20 datasheet, PDF - EEWORLD Datasheet

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33LV408RPFE-20: DescriptionStandard SRAM, 512KX8, 20ns, CMOS, DFP-32; Categorystorage storage; File Size176KB，14 Pages; ManufacturerMaxwell Technologies Inc.

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33LV408RPFE-20 Overview

Standard SRAM, 512KX8, 20ns, CMOS, DFP-32

33LV408RPFE-20 Parametric

Parameter Name	Attribute value
Maker	Maxwell Technologies Inc.
Parts packaging code	DFP
package instruction	DFP,
Contacts	32
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	20 ns
JESD-30 code	R-XDFP-F32
length	23.622 mm
memory density	4194304 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	512KX8
Package body material	UNSPECIFIED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	3.937 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	2.97 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
width	16.383 mm

33LV408RPFE-20 Preview

33LV408

4 Megabit (512K x 8-Bit)

CMOS SRAM

33LV408

Memory

Logic Diagram

EATURES

• R

-P

® Technology radiation-hardened against natural

space radiation

• 524,288 x 8 bit organization

· Total dose hardness:

- > 100 krad (Si), depending upon space mission

• Excellent Single Event Effect

· - SEL

: > 68 MeV/mg/cm

· - SEU

: = 3 MeV/mg/cm

•

- SEU saturated cross section: 6E-9 cm

/bit

Package:

- 32-Pin R

-P

® flat packFast access time:

- 20, 25, 30 ns maximum times available

Single 5V + 10% power supply

Fully static operation

- No clock or refresh required

Three state outputs

TTL compatible inputs and outputs

Low power:

- Standby: 60 mA (TTL); 10 mA (CMOS)

- Operation: 180 mA (20 ns); 170 mA (25 ns);

160 mA (30 ns)

ESCRIPTION

Maxwell Technologies’ 33LV408 high-density 4 Megabit

SRAM microcircuit features a greater than 100 krad (Si) total

dose tolerance, depending upon space mission. Using Max-

well’s radiation-hardened R

-P

® packaging technology, the

33LV408 realizes a high density, high performance, and low

power consumption. Its fully static design eliminates the need

for external clocks, while the CMOS circuitry reduces power

consumption and provides higher reliability. The 33LV408 is

equipped with eight common input/output lines, chip select

and output enable, allowing for greater system flexibility and

eliminating bus contention. The 33LV408 features the same

advanced 512K x 8-bit SRAM, high-speed, and low-power

demand as the commercial counterpart.

Maxwell Technologies' patented R

-P

packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-

age. It eliminates the need for box shielding while providing

the required radiation shielding for a lifetime in orbit or space

mission. In a GEO orbit, R

-P

provides greater than 100

krad (Si) radiation dose tolerance. This product is available

with screening up to Class S.

•

11.05.02 REV 1

All data sheets are subject to change without notice

(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com

4 Megabit (512K x 8-Bit) CMOS SRAM

ABLE

1. P

INOUT

ESCRIPTION

12-5, 27, 26, 23, 25, 4,

28, 3, 31, 2, 30, 1

13-15, 17-21

YMBOL

A0-A18

I/O 1-I/O 8

ESCRIPTION

Address Inputs

Write Enable

Chip Select

Output Enable

Data Inputs/Outputs

Power (+5.0V)

Ground

33LV408

ABLE

2. 33LV408 A

BSOLUTE

AXIMUM

ATINGS

Memory

ARAMETER

Voltage on V

supply relative to V

Voltage on any pin relative to V

Power Dissipation

Storage Temperature

Operating Temperature

YMBOL

, V

OUT

-0.5

-65

-55

7.0

+0.5

1.0

+150

+125

NIT

ABLE

3. D

ELTA

IMITS

ARAMETER

ARIATION

±10% of stated vaule in Table 6

11.05.02 REV 1

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) CMOS SRAM

ABLE

4. 33LV408 R

ECOMMENDED

PERATING

ONDITIONS

= 3.3 + 10%, T

= -55

+125

UNLESS OTHERWISE NOTED

)

ARAMETER

Supply Voltage

Ground

Input High Voltage

Input Low Voltage

Thermal Impedance

1. V

(max) = V

+2.0V ac (pulse width < 10 ns) for I < 20 mA

(min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA

YMBOL

4.5

2.2

-0.5

33LV408

5.5

+0.5

0.8

1.21

NIT

°C/W

ABLE

5. 33LV408 C

APACITANCE

(f = 1.0 MH

, dV = 3.3 V, T

= 25

ARAMETER

Input Capacitance

CS1 - CS4,

OE, WE

I/O0-7, I/O8-15, I/O16-23, I/O24-31

Input / Output Capacitance

1. Guaranteed by design.

YMBOL

EST

ONDITIONS

= 0 V

OUT

I/O

= 0 V

NITS

Memory

ABLE

6. 33LV408 DC E

LECTRICAL

HARACTERISTICS

= 3.3V + 10%, T

= -55

+125

UNLESS OTHERWISE SPECIFIED

)

ARAMETER

Input Leakage Current

Output Leakage Current

Output Low Voltage

Output High Voltage

Operating Current

-20

-25

-30

Standby Power Supply

Current

Input Capacitance

YMBOL

ONDITION

= V

to V

CS=V

or OE=V

or WE=V

OUT

to V

= 8mA

= -4mA

Min cycle, 100% Duty, CS=V

, I

OUT

=0mA,

= V

or V

UBGROUPS

1, 2, 3

180

170

160

-2

2.4

0.4

NIT

µA

CS = V

, Min Cycle

= 0V, f = 1MHz, T

= 25 °C

11.05.02 REV 1

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) CMOS SRAM

ABLE

6. 33LV408 DC E

LECTRICAL

HARACTERISTICS

= 3.3V + 10%, T

= -55

+125

UNLESS OTHERWISE SPECIFIED

)

ARAMETER

Output Capacitance

1. Guaranteed by design.

YMBOL

ONDITION

I/O

= 0V

UBGROUPS

1, 2, 3

33LV408

NIT

ABLE

7. 33LV408 AC O

PERATING

ONDITIONS AND

HARACTERISTICS

= 3.3 + 10%, T

= -55

+125

UNLESS OTHERWISE NOTED

)

ARAMETER

Input Pulse Level

Output Timing Measurement Reference Level

Input Rise/Fall Time

Input Timing Measurement Reference Level

0.0

3.0

1.5

3.0

1.5

NITS

Memory

ABLE

8. 33LV408 AC C

HARACTERISTICS FOR

EAD

YCLE

= 3.3V + 10%, T

= -55

+125

UNLESS OTHERWISE SPECIFIED

)

ARAMETER

Read Cycle Time

-20

-25

-30

Address Access Time

-20

-25

-30

Chip Select Access Time

-20

-25

-30

Output Enable to Output Valid

-20

-25

-30

Chip Enable to Output in Low-Z

-20

-25

-30

Output Enable to Output in Low-Z

-20

-25

-30

YMBOL

UBGROUPS

9, 10, 11

OLZ

9, 10, 11

NIT

11.05.02 REV 1

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) CMOS SRAM

ABLE

8. 33LV408 AC C

HARACTERISTICS FOR

EAD

YCLE

= 3.3V + 10%, T

= -55

+125

UNLESS OTHERWISE SPECIFIED

)

ARAMETER

Chip Deselect to Output in High-Z

-20

-25

-30

Output Disable to Output in High-Z

-20

-25

-30

Output Hold from Address Change

-20

-25

-30

Chip Select to Power Up Time

-20

-25

-30

Chip Select to Power Down Time

-20

-25

-30

YMBOL

UBGROUPS

9, 10, 11

OHZ

9, 10, 11

33LV408

NIT

Memory

ABLE

9. 33LV408 F

UNCTIONAL

ESCRIPTION

1. X = don’t care.

ODE

Not Select

Output Disable

Read

Write

I/O P

High-Z

OUT

UPPLY

URRENT

, I

SB1

ABLE

10. 33LV408 AC C

HARACTERISTICS FOR

RITE

YCLE

= 3.3V + 10%, T

= -55

+125

UNLESS OTHERWISE SPECIFIED

)

ARAMETER

Write Cycle Time

-20

-25

-30

YMBOL

UBGROUPS

9, 10, 11

NIT

11.05.02 REV 1

All data sheets are subject to change without notice

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