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HS9-81C56RH

Description
256X8 MULTI-PORT SRAM, 250ns, CDFP42
Categorystorage    storage   
File Size85KB,14 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
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HS9-81C56RH Overview

256X8 MULTI-PORT SRAM, 250ns, CDFP42

HS9-81C56RH Parametric

Parameter NameAttribute value
MakerRenesas Electronics Corporation
package instruction,
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time250 ns
Other featuresPORT-C CAN BE USED AS EITHER INPUT PORT, OUTPUT PORT OR AS CONTROL SIGNALS FOR PORT A & B
JESD-30 codeR-CDFP-F42
memory density2048 bit
Memory IC TypeMULTI-PORT SRAM
memory width8
Number of functions1
Number of ports3
Number of terminals42
word count256 words
character code256
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize256X8
Output characteristics3-STATE
ExportableNO
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formFLATPACK
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formFLAT
Terminal locationDUAL
HS-81C55RH,
HS-81C56RH
March 1996
Radiation Hardened
256 x 8 CMOS RAM
Description
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system. The
RAM portion is designed as 2048 static cells organized as 256
x 8. A maximum post irradiation access time of 500ns allows
the HS-81C55/56RH to be used with the HS-80C85RH CPU
without any wait states. The HS-81C55RH requires an active
low chip enable while the HS-81C56RH requires an active high
chip enable. These chips are designed for operation utilizing a
single 5V power supply.
Features
• Devices QML Qualified in Accordance with
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95818 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 10
5
RAD(Si)
- Transient Upset > 1 x 10
8
RAD(Si)/s
- Latch-Up Free > 1 x 10
12
RAD(Si)/s
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current 200µA Max
• Low Operating Current 2mA/MHz
• Completely Static Design
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55
o
C to +125
o
C
Functional Diagram
IO/M
AD0 - AD7
CE OR CE†
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
†81C55RH
= CE
81C56RH = CE
TIMER
C
PORT C
8
PC0 - PC5
VDD (10V)
GND
256 x 8
STATIC
RAM
A
PORT A
8
PA0 - PA7
PORT B
B
8
PB0 - PB7
Ordering Information
PART NUMBER
5962R9XXXX01QRC
5962R9XXXX01VRC
5962R9XXXX01QXC
5962R9XXXX01VXC
5962R9XXXX02QRC
5962R9XXXX02VRC
5962R9XXXX02QXC
5962R9XXXX02VXC
HS1-81C55RH/Sample
HS9-81C55RH/Sample
HS1-81C56RH/Sample
HS9-81C56RH/Sample
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
Sample
Sample
Sample
Sample
PACKAGE
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518056
3039.1

HS9-81C56RH Related Products

HS9-81C56RH 5962R9XXXX01VXC 5962R9XXXX02VRC 5962R9XXXX01QXC 5962R9XXXX02QXC 5962R9XXXX02QRC 5962R9XXXX02VXC HS9-81C55RH
Description 256X8 MULTI-PORT SRAM, 250ns, CDFP42 22 I/O, PIA-GENERAL PURPOSE, CDFP42, CERAMIC, FP-42 22 I/O, PIA-GENERAL PURPOSE, CDIP40, SIDE BRAZED, DIP-40 22 I/O, PIA-GENERAL PURPOSE, CDFP42, CERAMIC, FP-42 22 I/O, PIA-GENERAL PURPOSE, CDFP42, CERAMIC, FP-42 22 I/O, PIA-GENERAL PURPOSE, CDIP40, SIDE BRAZED, DIP-40 22 I/O, PIA-GENERAL PURPOSE, CDFP42, CERAMIC, FP-42 256X8 MULTI-PORT SRAM, 250ns, CDFP42
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknow
ECCN code 3A001.A.2.C EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 3A001.A.2.C
JESD-30 code R-CDFP-F42 R-CDFP-F42 R-CDIP-T40 R-CDFP-F42 R-CDFP-F42 R-CDIP-T40 R-CDFP-F42 R-CDFP-F42
Number of ports 3 3 3 3 3 3 3 3
Number of terminals 42 42 40 42 42 40 42 42
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLATPACK FLATPACK IN-LINE FLATPACK FLATPACK IN-LINE FLATPACK FLATPACK
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
surface mount YES YES NO YES YES NO YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
Terminal form FLAT FLAT THROUGH-HOLE FLAT FLAT THROUGH-HOLE FLAT FLAT
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Maker Renesas Electronics Corporation Renesas Electronics Corporation Renesas Electronics Corporation - Renesas Electronics Corporation - Renesas Electronics Corporation Renesas Electronics Corporation
Parts packaging code - DFP DIP DFP DFP DIP DFP -
Contacts - 42 40 42 42 40 42 -
JESD-609 code - e4 e4 e4 e4 e4 e4 -
Number of I/O lines - 22 22 22 22 22 22 -
Maximum supply voltage - 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V -
Minimum supply voltage - 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V -
Nominal supply voltage - 5 V 5 V 5 V 5 V 5 V 5 V -
Terminal surface - GOLD GOLD GOLD GOLD GOLD GOLD -
total dose - 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V -
uPs/uCs/peripheral integrated circuit type - PARALLEL IO PORT, GENERAL PURPOSE PARALLEL IO PORT, GENERAL PURPOSE PARALLEL IO PORT, GENERAL PURPOSE PARALLEL IO PORT, GENERAL PURPOSE PARALLEL IO PORT, GENERAL PURPOSE PARALLEL IO PORT, GENERAL PURPOSE -
Base Number Matches - 1 1 1 1 1 - -
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