HS9-81C55RH-8 datasheet, PDF - EEWORLD Datasheet

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HS9-81C55RH-8: Description256X8 MULTI-PORT SRAM, CDFP42, CERAMIC, DFP-42; Categorystorage storage; File Size113KB，11 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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HS9-81C55RH-8 Overview

256X8 MULTI-PORT SRAM, CDFP42, CERAMIC, DFP-42

HS9-81C55RH-8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	DFP
package instruction	DFP,
Contacts	42
Reach Compliance Code	not_compliant
ECCN code	3A001.A.2.C
Other features	TWO PROGRAMMABLE 8-BIT I/O PORTS
JESD-30 code	R-CDFP-F42
JESD-609 code	e0
length	26.925 mm
memory density	2048 bit
Memory IC Type	MULTI-PORT SRAM
memory width	8
Number of functions	1
Number of terminals	42
word count	256 words
character code	256
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	256X8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	2.54 mm
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
total dose	100k Rad(Si) V
width	16.255 mm

HS9-81C55RH-8 Preview

HS-81C55RH, HS-81C56RH

Data Sheet

August 2000

File Number

3039.2

Radiation Hardened 256 x 8 CMOS RAM

The HS-81C55/56RH are radiation hardened RAM and I/O

chips fabricated using the Intersil radiation hardened Self-

Aligned Junction Isolated (SAJI) silicon gate technology.

Latch-up free operation is achieved by the use of epitaxial

starting material to eliminate the parasitic SCR effect seen in

conventional bulk CMOS devices.

The HS-81C55/56RH is intended for use with the

HS-80C85RH radiation hardened microprocessor system.

The RAM portion is designed as 2048 static cells organized

as 256 x 8. A maximum post irradiation access time of

500ns allows the HS-81C55/56RH to be used with the

HS-80C85RH CPU without any wait states. The

HS-81C55RH requires an active low chip enable while the

HS-81C56RH requires an active high chip enable. These

chips are designed for operation utilizing a single 5V power

supply.

Speciﬁcations for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed here must be used when ordering.

Detailed Electrical Speciﬁcations for these devices are

contained in SMD 5962-96766. A “hot-link” is provided

on our homepage for downloading.

http://www.intersil.com/spacedefense/space.asp

Features

• Electrically Screened to SMD # 5962-96766

• QML Qualiﬁed per MIL-PRF-38535 Requirements

• Radiation Hardened EPI-CMOS

- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)

- Transient Upset . . . . . . . . . . . . . . . . . .>1 x 10

rad(Si)/s

- Latch-Up Free . . . . . . . . . . . . . . . . . . >1 x 10

rad(Si)/s

• Electrically Equivalent to Sandia SA 3001

• Pin Compatible with Intel 8155/56

• Bus Compatible with HS-80C85RH

• Single 5V Power Supply

• Low Standby Current . . . . . . . . . . . . . . . . . . . .200µA Max

• Low Operating Current . . . . . . . . . . . . . . . . . . . . 2mA/MHz

• Completely Static Design

• Internal Address Latches

• Two Programmable 8-Bit I/O Ports

• One Programmable 6-Bit I/O Port

• Programmable 14-Bit Binary Counter/Timer

• Multiplexed Address and Data Bus

• Self Aligned Junction Isolated (SAJI) Process

• Military Temperature Range . . . . . . . . . . . -55

C to 125

Ordering Information

ORDERING NUMBER

5962R9676601QXC

5962R9676601QYC

5962R9676601VXC

5962R9676601VYC

5962R9676602QXC

5962R9676602QYC

5962R9676602VXC

5962R9676602VYC

INTERNAL

MKT. NUMBER

HS1-81C55RH-8

HS9-81C55RH-8

HS1-81C55RH-Q

HS9-81C55RH-Q

HS1-81C56RH-8

HS9-81C56RH-8

HS1-81C56RH-Q

HS9-81C56RH-Q

TEMP. RANGE

(

-55 to 125

Functional Diagram

IO/M

AD0 - AD7

CE OR CE

†

ALE

RESET

TIMER CLK

TIMER OUT

TIMER

PORT C

PC0 - PC5

VDD (10V)

GND

256 x 8

STATIC

RAM

PORT A

PA0 - PA7

PORT B

PB0 - PB7

†

81C55RH = CE

81C56RH = CE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Corporation.

HS-81C55RH, HS-81C56RH

Pinouts

40 LEAD DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T40

TOP VIEW

PC3

PC4

TIMER IN

RESET

PC5

TIMER OUT

IO / M

CE or CE

†

40 VDD

39 PC2

38 PC1

37 PC0

36 PB7

35 PB6

34 PB5

33 PB4

32 PB3

31 PB2

30 PB1

29 PB0

28 PA7

27 PA6

26 PA5

25 PA4

24 PA3

23 PA2

22 PA1

21 PA0

PC3

PC4

TIMER IN

RESET

PC5

TIMER OUT

IO/M

CE OR CE

ALE

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

VDD

PC2

PC1

PC0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

INTERSIL OUTLINE K42.A

TOP VIEW

RD 9

WR 10

ALE 11

AD0 12

AD1 13

AD2 14

AD3 15

AD4 16

AD5 17

AD6 18

AD7 19

GND 20

†

81C55RH = CE

81C56RH = CE

HS-81C55RH, HS-81C56RH

Pin Descriptions

SYMBOL

RESET

TYPE

NAME AND FUNCTION

Reset:

Pulse provided by the HS-80C85RH to initialize the system (connect to HS-80C85RH RESET OUT).

Input high on this line resets the chip and initializes the three I/O ports to input mode. The width of RESET

pulse should typically be two HS-80C85RH clock cycle times.

Address/Data:

Three-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The

8-bit address is latched into the address latch inside the HS-81C55 and HS-81C56RH on the falling edge of

ALE. The address can be either for the memory section or the I/O section depending on the IO/M input. The

8-bit data is either written into the chip or read from the chip, depending on the WR or RD input signal.

Chip Enable:

On the HS-81C55RH, this pin is CE and is ACTIVE LOW. On the HS-81C56RH, this pin is CE

and is ACTIVE HIGH.

Read Control:

Input low on this line with the Chip Enable active enables and AD0 - AD7 buffers. If IO/M pin

is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O port or

command/status registers will be read to the AD bus.

Write Control:

Input low on this line with the Chip Enable active causes the data on the Address/Data bus to

be written to the RAM or I/O ports and command/status register, depending on IO/M.

Address Latch Enable:

This control signal latches both the address on the AD0 - AD7 lines and the state of

the Chip Enable and IO/M into the chip at the falling edge of ALE.

I/O Memory:

Selects memory if low and I/O and command/status registers if high.

Port A:

These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the

command register.

Port B:

These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the

command register.

Port C:

These 6 pins can function as either input port, output port, or as control signals for PA and PB.

Programming is done through the command register. When PC0 - PC5 are used as control signals, they will

provide the following:

PC0 - A INTR (Port A Interrupt)

PC1 - ABF (Port A Buffer Full)

PC2 - A STB (Port A Strobe)

PC3 - B INTR (Port B Interrupt)

PC4 - B BF (Port B Buffer Full)

PC5 - B STB (Port B Strobe)

Timer Input:

Input to the counter-timer.

Timer Output:

This output can be either a square wave or a pulse, depending on the timer mode.

Voltage:

+5V.

Ground:

Ground reference.

AD0 - AD7

I/O

CE or CE

ALE

IO/M

PA0 - PA7 (8)

PB0 - PB7 (8)

PC0 - PC7 (8)

I/O

TIMER IN

TIMER OUT

VDD

GND

HS-81C55RH, HS-81C56RH

Waveforms

READ

CE (81C55RH)

CE (81C56RH)

IO/M

tAD

0-7

tAL

ALE

tLL

tLC

tCC

tRV

tRIDE

tRD

tCL

tRDF

ADDRESS

tLA

DATA VALID

WRITE

CE (81C55RH)

CE (81C56RH)

IO/M

0-7

tAL

ALE

tLL

ADDRESS

tLA

tDW

DATA VALID

tCL

tLC

tCL

tCC

tWD

tRV

HS-81C55RH, HS-81C56RH

Waveforms

(Continued)

STROBED INPUT

tSBF

STROBED

tSS

INTR

tRDI

tSI

tRBE

tPSS

INPUT DATA

FROM PORT

tPHS

STROBED OUTPUT

tSBE

STROBE

tWBF

INTR

tWI

tWP

OUTPUT DATA

TO PORT

tSI

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HS9-81C55RH-8 Related Products

	HS9-81C55RH-8	HS9-81C56RH-Q	HS9-81C55RH-Q	HS9-81C56RH-8	HS1-81C56RH-Q	HS1-81C55RH-8	HS1-81C55RH-Q	HS1-81C56RH-8
Description	256X8 MULTI-PORT SRAM, CDFP42, CERAMIC, DFP-42	256X8 MULTI-PORT SRAM, CDFP42, CERAMIC, DFP-42	256X8 MULTI-PORT SRAM, CDFP42, CERAMIC, DFP-42	256X8 MULTI-PORT SRAM, CDFP42, CERAMIC, DFP-42	256X8 MULTI-PORT SRAM, CDIP40, SIDE BRAZED, CERAMIC, DIP-40	256X8 MULTI-PORT SRAM, CDIP40, SIDE BRAZED, CERAMIC, DIP-40	256X8 MULTI-PORT SRAM, CDIP40, SIDE BRAZED, CERAMIC, DIP-40	256X8 MULTI-PORT SRAM, CDIP40, SIDE BRAZED, CERAMIC, DIP-40
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	DFP	DFP	DFP	DFP	DIP	DIP	DIP	DIP
package instruction	DFP,	DFP,	DFP,	DFP,	DIP,	DIP,	DIP,	DIP,
Contacts	42	42	42	42	40	40	40	40
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Other features	TWO PROGRAMMABLE 8-BIT I/O PORTS	TWO PROGRAMMABLE 8-BIT I/O PORTS	TWO PROGRAMMABLE 8-BIT I/O PORTS	TWO PROGRAMMABLE 8-BIT I/O PORTS	TWO PROGRAMMABLE 8-BIT I/O PORTS	TWO PROGRAMMABLE 8-BIT I/O PORTS	TWO PROGRAMMABLE 8-BIT I/O PORTS	TWO PROGRAMMABLE 8-BIT I/O PORTS
JESD-30 code	R-CDFP-F42	R-CDFP-F42	R-CDFP-F42	R-CDFP-F42	R-CDIP-T40	R-CDIP-T40	R-CDIP-T40	R-CDIP-T40
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
memory density	2048 bit	2048 bit	2048 bit	2048 bit	2048 bit	2048 bit	2048 bit	2048 bit
Memory IC Type	MULTI-PORT SRAM	MULTI-PORT SRAM	MULTI-PORT SRAM	MULTI-PORT SRAM	MULTI-PORT SRAM	MULTI-PORT SRAM	MULTI-PORT SRAM	MULTI-PORT SRAM
memory width	8	8	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	42	42	42	42	40	40	40	40
word count	256 words	256 words	256 words	256 words	256 words	256 words	256 words	256 words
character code	256	256	256	256	256	256	256	256
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
organize	256X8	256X8	256X8	256X8	256X8	256X8	256X8	256X8
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP	DFP	DFP	DFP	DIP	DIP	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK	IN-LINE	IN-LINE	IN-LINE	IN-LINE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.54 mm	2.54 mm	2.54 mm	2.54 mm	5.72 mm	5.72 mm	5.72 mm	5.72 mm
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	FLAT	FLAT	FLAT	FLAT	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
total dose	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V
width	16.255 mm	16.255 mm	16.255 mm	16.255 mm	15.24 mm	15.24 mm	15.24 mm	15.24 mm

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