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74AUP1G332GW

Description
OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6
Categorylogic    logic   
File Size196KB,19 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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74AUP1G332GW Overview

OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6

74AUP1G332GW Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionTSSOP,
Reach Compliance Codecompliant
seriesAUP/ULP/V
JESD-30 codeR-PDSO-G6
JESD-609 codee3
length2 mm
Logic integrated circuit typeOR GATE
Humidity sensitivity level1
Number of functions1
Number of entries3
Number of terminals6
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)18.7 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)0.8 V
Nominal supply voltage (Vsup)1.1 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width1.25 mm
74AUP1G332
Low-power 3-input OR-gate
Rev. 5 — 4 July 2012
Product data sheet
1. General description
The 74AUP1G332 provides a single 3-input OR gate.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C

74AUP1G332GW Related Products

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Description OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6 OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6 OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6 OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6 OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6 OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6 OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6 OR Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6
Is it Rohs certified? conform to conform to conform to conform to conform to conform to conform to conform to
package instruction TSSOP, VSON, VSON, VSON, SON, VSON, VSON, VSON,
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
series AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V
JESD-30 code R-PDSO-G6 R-PDSO-N6 R-PDSO-N6 S-PDSO-N6 R-PDSO-N6 S-PDSO-N6 S-PDSO-N6 R-PDSO-N6
JESD-609 code e3 e3 e3 e3 e3 e3 e3 e3
length 2 mm 1.45 mm 1.45 mm 1 mm 1 mm 1 mm 1 mm 1.45 mm
Logic integrated circuit type OR GATE OR GATE OR GATE OR GATE OR GATE OR GATE OR GATE OR GATE
Humidity sensitivity level 1 1 1 1 1 1 1 1
Number of functions 1 1 1 1 1 1 1 1
Number of entries 3 3 3 3 3 3 3 3
Number of terminals 6 6 6 6 6 6 6 6
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP VSON VSON VSON SON VSON VSON VSON
Package shape RECTANGULAR RECTANGULAR RECTANGULAR SQUARE RECTANGULAR SQUARE SQUARE RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd) 18.7 ns 18.7 ns 18.7 ns 18.7 ns 18.7 ns 18.7 ns 18.7 ns 18.7 ns
Maximum seat height 1.1 mm 0.5 mm 0.5 mm 0.35 mm 0.35 mm 0.5 mm 0.5 mm 0.5 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V
Nominal supply voltage (Vsup) 1.1 V 1.1 V 1.1 V 1.1 V 1.1 V 1.1 V 1.1 V 1.1 V
surface mount YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface Tin (Sn) Tin (Sn) Tin (Sn) Tin (Sn) Tin (Sn) Tin (Sn) Tin (Sn) Tin (Sn)
Terminal form GULL WING NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD
Terminal pitch 0.65 mm 0.5 mm 0.5 mm 0.35 mm 0.3 mm 0.35 mm 0.35 mm 0.5 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
width 1.25 mm 1 mm 1 mm 1 mm 0.9 mm 1 mm 1 mm 1 mm
Maker Nexperia Nexperia - - - Nexperia Nexperia Nexperia
Peak Reflow Temperature (Celsius) 260 - 260 260 260 260 - -
Certification status Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified - -
Maximum time at peak reflow temperature 30 - 30 30 30 30 - -
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