82V3358TFG datasheet, PDF - EEWORLD Datasheet

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82V3358TFG: DescriptionTQFP-64, Tray; CategoryWireless rf/communication Telecom circuit; File Size1MB，140 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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TQFP-64, Tray

82V3358TFG Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	LQFP-64
Contacts	64
Manufacturer packaging code	PPG64
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	10 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP64,.47SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	0.464 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm

82V3358TFG Preview

SYNCHRONOUS ETHERNET

WAN PLL

IDT82V3358

Version 4

May 19, 2009

6024 Silver Creek Valley Road, San Jose, CA 95138

Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775

Printed in U.S.A.

DISCLAIMER

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos-

sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry

described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other

rights, of Integrated Device Technology, Inc.

LIFE SUPPORT POLICY

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe-

cuted between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in

accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its

safety or effectiveness.

Table of Contents

FEATURES .............................................................................................................................................................................. 9

HIGHLIGHTS.................................................................................................................................................................................................... 9

MAIN FEATURES ............................................................................................................................................................................................ 9

OTHER FEATURES ......................................................................................................................................................................................... 9

APPLICATIONS....................................................................................................................................................................... 9

DESCRIPTION....................................................................................................................................................................... 10

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11

1 PIN ASSIGNMENT ........................................................................................................................................................... 12

2 PIN DESCRIPTION .......................................................................................................................................................... 13

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 17

3.1

3.2

3.3

RESET ........................................................................................................................................................................................................... 17

MASTER CLOCK .......................................................................................................................................................................................... 17

INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 18

3.3.1 Input Clocks .................................................................................................................................................................................... 18

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 18

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 19

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 20

3.5.1 Activity Monitoring ......................................................................................................................................................................... 20

3.5.2 Frequency Monitoring ................................................................................................................................................................... 21

3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 22

3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 22

3.6.2 Forced Selection ............................................................................................................................................................................ 23

3.6.3 Automatic Selection ....................................................................................................................................................................... 23

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 24

3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 24

3.7.1.1 Fast Loss .......................................................................................................................................................................... 24

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 24

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 24

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 24

3.7.2 Locking Status ............................................................................................................................................................................... 24

3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 25

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 26

3.8.1 Input Clock Validity ........................................................................................................................................................................ 26

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 26

3.8.2.1 Revertive Switch ............................................................................................................................................................... 26

3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 27

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 27

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 28

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 28

3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 30

3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 31

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 31

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 31

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 31

3.10.1.3 Locked Mode .................................................................................................................................................................... 31

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 31

Table of Contents

May 19, 2009

IDT82V3358

SYNCHRONOUS ETHERNET WAN PLL

3.11

3.12

3.13

3.14

3.15

3.16

3.17

4 MICROPROCESSOR INTERFACE .................................................................................................................................. 45

5 JTAG ................................................................................................................................................................................ 47

6 PROGRAMMING INFORMATION .................................................................................................................................... 48

6.1

6.2

REGISTER MAP ............................................................................................................................................................................................ 48

REGISTER DESCRIPTION ........................................................................................................................................................................... 53

6.2.1 Global Control Registers ............................................................................................................................................................... 53

6.2.2 Interrupt Registers ......................................................................................................................................................................... 61

6.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 65

6.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 76

6.2.5 T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 87

6.2.6 T0 / T4 DPLL State Machine Control Registers ........................................................................................................................... 91

6.2.7 T0 / T4 DPLL & APLL Configuration Registers ............................................................................................................................ 93

6.2.8 Output Configuration Registers .................................................................................................................................................. 106

6.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 112

6.2.10 Synchronization Configuration Registers ................................................................................................................................. 114

JUNCTION TEMPERATURE ...................................................................................................................................................................... 116

EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 116

HEATSINK EVALUATION .......................................................................................................................................................................... 116

ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 117

RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 117

I/O SPECIFICATIONS ................................................................................................................................................................................. 118

8.3.1 CMOS Input / Output Port ............................................................................................................................................................ 118

8.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 119

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 31

3.10.1.5 Holdover Mode ................................................................................................................................................................. 31

3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 32

3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 32

3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 32

3.10.1.5.4 Manual ........................................................................................................................................................... 32

3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 32

3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 32

3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 32

3.10.2.1 Free-Run Mode ................................................................................................................................................................ 32

3.10.2.2 Locked Mode .................................................................................................................................................................... 32

3.10.2.3 Holdover Mode ................................................................................................................................................................. 32

T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 34

3.11.1 PFD Output Limit ............................................................................................................................................................................ 34

3.11.2 Frequency Offset Limit .................................................................................................................................................................. 34

3.11.3 PBO (T0 only) ................................................................................................................................................................................. 34

3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 34

3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 34

3.11.5.1 T0 Path ............................................................................................................................................................................. 34

3.11.5.2 T4 Path ............................................................................................................................................................................. 35

T0 / T4 APLL ................................................................................................................................................................................................. 36

OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 36

3.13.1 Output Clocks ................................................................................................................................................................................. 36

3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 40

INTERRUPT SUMMARY ............................................................................................................................................................................... 42

T0 AND T4 SUMMARY ................................................................................................................................................................................. 42

POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 43

LINE CARD APPLICATION .......................................................................................................................................................................... 44

7 THERMAL MANAGEMENT ........................................................................................................................................... 116

7.1

7.2

7.3

8.1

8.2

8.3

8 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 117

Table of Contents

May 19, 2009

IDT82V3358

SYNCHRONOUS ETHERNET WAN PLL

PACKAGE DIMENSIONS.................................................................................................................................................... 134

ORDERING INFORMATION................................................................................................................................................ 139

8.4

8.5

8.6

8.7

8.3.2.1 PECL Input / Output Port ................................................................................................................................................ 119

8.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 121

8.3.2.3 Single-Ended Input for Differential Input ........................................................................................................................ 122

JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 123

OUTPUT WANDER GENERATION ............................................................................................................................................................ 126

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 127

OUTPUT CLOCK TIMING ........................................................................................................................................................................... 128

Table of Contents

May 19, 2009

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82V3358TFG Related Products

	82V3358TFG	82V3358TFG8
Description	TQFP-64, Tray	TQFP-64, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TQFP	TQFP
Contacts	64	64
Manufacturer packaging code	PPG64	PPG64
Reach Compliance Code	compliant	compliant
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT

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