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Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> UC1633J
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UC1633J

Description
PLL Frequency Synthesizer, BIPolar, CDIP16, CERAMIC, DIP-16
CategoryAnalog mixed-signal IC    The signal circuit   
File Size602KB，9 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric View All

UC1633J Overview

PLL Frequency Synthesizer, BIPolar, CDIP16, CERAMIC, DIP-16

UC1633J Parametric

Parameter NameAttribute value
MakerRochester Electronics
package instructionDIP,
Reach Compliance Codeunknown
Other featuresMOTION CONTROL APPLICATIONS
Analog Integrated Circuits - Other TypesPLL FREQUENCY SYNTHESIZER
JESD-30 codeR-GDIP-T16
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)15 V
Minimum supply voltage (Vsup)8 V
Nominal supply voltage (Vsup)12 V
surface mountNO
technologyBIPOLAR
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm

UC1633J Preview

UC1633
UC2633
UC3633
Phase Locked Frequency Controller
FEATURES
•
•
•
•
•
•
•
•
Precision Phase Locked Frequency
Control System
DESCRIPTION
The UC1633 family of integrated circuits was designed for use in phase
locked frequency control loops. While optimized for precision speed
control of DC motors, these devices are universal enough for most ap-
Crystal Oscillator
plications that require phase locked control. A precise reference fre-
Programmable Reference Frequency
quency can be generated using the device’s high frequency oscillator
Dividers
and programmable frequency dividers. The oscillator operates using a
Phase Detector with Absolute Frequency broad range of crystals, or, can function as a buffer stage to an external
frequency source.
Steering
Digital Lock Indicator
Double Edge Option on the Frequency
Feedback Sensing Amplifier
Two High Current Op-Amps
5V Reference Output
The phase detector on these integrated circuits compares the refer-
ence frequency with a frequency/phase feedback signal. In the case of
a motor, feedback is obtained at a hall output of other speed detection
device. This signal is buffered by a sense ampilfier that squares up the
signal as it goes into the digital phase detector. The phase detector re-
sponds proportionally to the phase error between the reference and the
sense amplifier output. This phase detector includes absolute fre-
quency steering to provide maximum drive signals when any frequency
error exists. This feature allows optimum start-up and lock times to be
realized.
Two op-amps are included that can be configured to provide necessary
loop filtering. The outputs of the op-amps will source or sink in excess
of 16mA, so they can provide a low impedence control signal to driving
circuits.
Additional features include a double edge option on the sense amplifier
that can be used to double the loop reference frequency for increased
loop bandwidths. A digital lock signal is provided that indicates when
there is zero frequency error, and a 5V reference output allows DC op-
erating levels to be accurately set.
BLOCK DIAGRAM
4/97
1
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (+V
IN
) . . . . . . . . . . . . . . . . . . . . . . . . +20V
Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . -30mA
Op-Amp Output Currents . . . . . . . . . . . . . . . . . . . . . . . .
±
30mA
Op-Amp Input Voltages . . . . . . . . . . . . . . . . . . . . . -.3V to +20V
Phase Detector Output Current . . . . . . . . . . . . . . . . . . .
±
10mA
Lock Indicator Output Current . . . . . . . . . . . . . . . . . . . . +15mA
Lock Indicator Output Voltage . . . . . . . . . . . . . . . . . . . . . . +20V
Divide Select Input Voltages . . . . . . . . . . . . . . . . . -.3V to +10V
Double Edge Disable Input Voltage . . . . . . . . . . . . -.3V to +10V
Oscillator Input Voltage . . . . . . . . . . . . . . . . . . . . . . -.3V to +5V
Sense Amplifier Input Voltage . . . . . . . . . . . . . . . . .3V to +20V
Power Dissipation at T
A
= 25°C (Note 2 . . . . . . . . . . . 1000mW
Power dissipation at T
C
= 25°C (Note 2) . . . . . . . . . . . 2000mW
Operating Junction Temperature . . . . . . . . . . . -55°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C
UC1633
UC2633
UC3633
Note1: Voltages are referenced to ground, (Pin 16). Currents
are positive into, negative out of, the specified terminals.
Note 2: Consult Packaging Section of Databook for thermal limi-
tations and considerations of package.
CONNECTION DIAGRAMS
PLCC-20 (TOP VIEW)
Q Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
DIL-16 (TOP VIEW)
J or N Package
N/C
Div 4/5 Input
Div 2/4/8 Input
Lock Indicator Output
Phase Detector Output
N/C
Dbl Edge Disable Input
Sense Amp Input
5V Ref Output
Loop Amp Inv Input
N/C
Loop Amp Output
Aux Amp Non-Inv Input
Aux Amp Inv Input
Aux Amp Output
N/C
+V
IN
OSC Output
OSC Input
Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ELECTRICAL CHARACTERISTICS:
(Unless otherwise stated, these specifications apply for T
A
= 0°C to +70°C for the
PARAMETER
Supply Current
Reference
Output Voltage (V
REF
)
Load Regulation
Line Regulation
Short Circuit Current
Oscillator
DC Voltage Gain
Input DC Level (V
IB
)
Input Impedance (Note 3)
Output DC Level
Maximum Operating Frequency
Dividers
Maximum Input Frequency
Div. 4/5 Input Current
Div. 4/5 Threshold
Input = 1V
PP
at Oscillator Input
Input = 5V (Div. by 4)
Input = 0V (Div. by 5)
-5.0
0.5
10
150
0.0
1.6
500
5.0
2.2
Oscillator Input to Oscillator Output
Oscillator Input Pin Open, T
J
= 25°C
V
IN
= V
IB
±
0.5V, T
J
= 25°C
Oscillator Input Pin Open, T
J
= 25°C
12
1.15
1.3
1.2
10
16
1.3
1.6
1.4
20
1.45
1.9
1.6
I
OUT
= 0V to 7mA
+V
IN
= 8V to 15V
V
OUT
= 0V
12
4.75
5.0
5.0
2.0
30
5.25
20
20
+V
IN
= 15V
TEST CONDITIONS
MIN.
TYP.
20
UC3633, -25°C to +85°C for the UC2633, -55°C to +125°C for the UC1633, +V
IN
=
12V; T
A
=T
J
.)
MAX. UNITS
28
mA
V
mV
mV
mA
dB
V
kΩ
V
MHz
MHz
µA
µA
V
Note 3: These impedence levels will vary with T
J
at about 1700ppm/°C
2
UC1633
UC2633
UC3633
(Unless otherwise stated, these specifications apply for T
A
= 0°C to +70°C for the UC3633,
ELECTRICAL
CHARACTERISTICS (cont.):
-25°C to +85°C for the UC2633, -55°C to +125°C for the UC1633, +V
IN
= 12V; T
A
=T
J
.)
PARAMETER
Dividers (cont.)
Div. 2/4/8 Input Current
Div. 2/4/8 Open Circuit Voltage
Div. by 2 Threshold
Div. by 4 Threshold
Div. by 8 Threshold
Sense Amplifier
Threshold Voltage
Threshold Hysteresis
Input Bias Current
Double Edge Disable Input
Input Current
Threshold Voltage
Phase Detector
High Output Level
Low Output Level
Mid Output Level
High Level Maximum Source Current
Low Level Maximum Sink Current
Mid Level Output Impedance (Note 3)
Lock Indicator Output
Saturation Voltage
Leakage Current
Loop Amplifier
NON INV. Reference Voltage
Input Bias Current
AVOL
PSRR
Short Circuit Current
Auxiliary Op-Amp
Input Offset Voltage
Input Bias Current
Input Offset Current
AVOL
PSRR
CMRR
Short Circuit Current
+V
IN
= 8V to 15V
V
CM
= 0V to 10V
Source, V
OUT
= 0V
Sink, V
OUT
= 5V
V
CM
= 2.5V
V
CM
= 2.5V
V
CM
= 2.5V
70
70
70
16
16
-0.8
-0.2
.01
120
100
100
35
30
0.1
8
mV
µA
µA
dB
dB
dB
mA
mA
+V
IN
= 8V to 15V
Source, V
OUT
= 0V
Sink, V
OUT
= 5V
Percent of V
REF
Input = 2.5V
47
-0.8
60
70
16
16
50
-0.2
75
100
35
30
53
%
µA
dB
dB
mA
mA
Freq. Error, I
OUT
= 5mA
Zero Freq. Error, V
OUT
= 15V
0.3
0.1
0.45
1.0
V
µA
Positive Phase/Freq. Error, Volts Below V
REF
Negative Phase/Freq. Error
Zero Phase/Freq. Error, Percent of V
REF
V
OUT
= 4.3V
V
OUT
= 0.7V
I
OUT
= -200 to +200µA, T
J
= 25°C
47
2.0
2.0
4.5
0.2
0.2
50
8.0
5.0
6.0
7.5
0.5
0.5
53
V
V
%
mA
mA
kΩ
Input = 5V (Disabled)
Input = 0V (Enabled)
-5.0
0.5
150
0.0
1.6
500
5.0
2.2
µA
µA
v
Input = 1.5V
-1.0
Percent of V
REF
27
30
10
-0.2
33
%
mV
µA
Volts Below V
REF
Input = 5V (Div. by 8)
Input = 0V (Div. by 2)
Input Current = 0µA (Div. by 4)
-500
1.5
0.20
1.5
0.20
0.8
150
-150
2.5
0.8
3.5
3.5
500
µA
µA
V
V
V
V
TEST CONDITIONS
MIN.
TYP.
MAX. UNITS
Note 3: These impedence levels will vary with T
J
at about 1700ppm/°C
3
APPLICATION AND OPERATING INFORMATION
Determining the Oscillator Frequency
The frequency at the oscillator is determined by the de-
sired RPM of the motor, the divide ratio selected, the
number of poles in the motor, and the state of the double
edge select pin.
f
OSC
(Hz) = (Divide Ratio)
•
(Motor RPM)
•
(1/60 SEC/MIN)
•
(No. of Rotor Poles/2)
•
(x 2 if Pin 5 Low)
UC1633
UC2633
UC3633
The resulting reference frequency appearing at the phase
detector inputs is equal to the oscillator frequency divided
by the selected divide ratio. If the double edge option is
used, (Pin 5 low), the frequency of the sense amplifier in-
put signal is doubled by responding to both the rising and
falling edges of the input signal. Using this option, the loop
reference frequency can be doubled for a given motor
RPM.
Recommended Oscillator Configuration Using AT Cut Quartz Crystal
External Reference Frequency Input
Method for Deriving Rotation Feedback Signal from Analog Hall Effect Device
*This signal may require filtering if chopped mode drive scheme is used.
4
APPLICATION AND OPERATION INFORMATION
Phase Detector Operation
The phase detector on these devices is a digital circuit
that responds to the rising edges of the detector’s two in-
puts. The phase detector output has three states: a high,
5V state, a low, 0V state, and a middle, 2.5V state. In the
high and low states the output impedance of the detector
is low and the middle state output impedence is high, typi-
cally 6.0kΩ. When there is any static frequency difference
between the inputs, the detector output is fixed at its high
level if the +input (the sense amplifier signal) is greater in
frequency, and fixed at its low level if the -input (the refer-
ence frequency signal) is greater in frequency.
When the frequencies of the two inputs to the detector
are equal, the phase detector switches between its middle
state and either the high or low states, depending on the
relative phase of the two signals. If the +input is leading in
phase then, during each period of the input frequency, the
detector output will be high for a time equal to the time dif-
ference between the rising edges of the inputs, and will
be at its middle level for the remainder of the period. If the
phase relationship is reversed, then the detector will go
low for a time proportional to the phase difference of the
inputs. The resulting gain of the phase detector. kø, is
UC1633
UC2633
UC3633
5V/4π radians or about 0.4V/radian. The dynamic range of
the detector is
±
2π radians.
The operation of the phase detector is illustrated in the
figures below. The upper figure shows typical voltage
waveforms seen at the detector output for leading and
lagging phase conditions. The lower figure is a state dia-
gram of the phase detector logic. In this figure, the circles
represent the 10 possible states of the logic, and the con-
necting arrows represent the transition events/paths to
and from these states. Transition arrows that have a clock-
wise rotation are the result of a rising edge on the +input,
and conversely, those with counter-clockwise rotation are
tied to the rising edge of the -input signal.
The normal operational states of the logic are 6 and 7 for
positive phase error, 1 and 2 for a negative phase error.
States 8 and 9 occur during positive frequency error, 3
and 4 during negative frequency error. States 5 and 10
occur only as the inputs cross over from the frequency er-
ror to a normal phase error only condition. The level of the
phase detector output is determined by the logic state as
defined in the state diagram figure. The lock indicator out-
put is high, off, when the detector is in states 1, 2, 6, or 7.
Typical Phase Detector Output Waveforms
Phase Detector State Diagram
5
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