HCSL/ LVCMOS Clock Generator
8413S12BI-126
Data Sheet
General Description
The 8413S12BI-126 is a PLL-based clock generator. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express, sRIO, XAUI, SerDes reference
clocks and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs.
The output frequencies are generated from a 25MHz external input
source or an external 25MHz parallel resonant crystal. The industrial
temperature range of the 8413S12BI-126 supports
telecommunication, networking, and storage requirements.
Features
•
•
•
•
•
•
•
•
•
•
Ten selectable 100MHz and 156.25MHz clocks for PCI Express,
sRIO and GbE, HCSL interface levels
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15
output impedance
Selectable external crystal or differential (single-ended)
input source
Crystal oscillator interface designed for 25MHz, parallel
resonant crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
PCI Express (2.5Gb/S), Gen 2 (5Gb/s) and Gen 3 (8Gb/s)
jitter compliant
Full 3.3V power supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Applications
•
•
•
•
•
•
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•
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
V
DDO_E
V
DDO_F
OE_E
nQE1
nQE0
Pin Assignment
QF
nc
nc
nc
nc
nc
nc
nc
nc
nMR
QE1
QE0
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
nc
GND
FSEL_A0
nc
FSEL_B0
nc
FSEL_C0
nc
FSEL_D0
nc
FSEL_E0
V
DDA
nc
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54
53
52
51
50
nc
V
DD
IREF
OE_D
nQD1
QD1
nQD0
QD0
V
DDO_D
V
DDO_C
nQC1
QC1
nQC0
QC0
OE_C
V
DD
GND
nc
8XXXXXX
49
48
47
8413S12BI-126
46
45
44
43
42
41
40
39
38
37
V
DDO_A
PLL_SEL
V
DDO_B
CLK
OE_A
OE_B
V
DD
nc
nCLK
QA0
QA1
QB0
nQA0
nQA1
nQB0
QB1
72-pin, 10mm x 10mm LQFP Package
©2016 Integrated Device Technology, Inc
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nQB1
nc
January 7, 2016
8413S12BI-126 Data Sheet
Block Diagram
nMR
Pulldown
OE_A
QA0
FSEL_A0
FSEL_B0
FSEL_C0
FSEL_D0
FSEL_E0
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Clock
Output
Control
Logic
0 = 100MHz
1 = 156.25MHz
nQA0
QA1
nQA1
QB0
0 = 100MHz
1 = 156.25MHz
QB0
QB1
QB1
QC0
PLL_SEL
REF_SEL
Pullup
Pullup
0 = 100MHz
1 = 156.25MHz
nQC0
QC1
nQC1
QD0
CLK
nCLK
Pulldown
Pullup/Pulldown
0
0
1
XTAL_IN
OSC
XTAL_OUT
IREF
50MHz
QF
0 = 100MHz
1 = 156.25MHz
VCO
1
QE0
nQE0
QE1
nQE1
0 = 100MHz
1 = 156.25MHz
nQD0
QD1
nQD1
OE_E
OE_D
OE_C
OE_B
©2016 Integrated Device Technology, Inc
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January 7, 2016
8413S12BI-126 Data Sheet
Pin Descriptions
Table 1. Pin Descriptions
Number
1, 18, 38
2
4
6
8
10
11
3, 5, 7, 9, 12,
13, 16, 19,
36, 37, 54,
55, 65, 66,
67, 68, 69,
70, 71, 72
14,
15
17
20, 39, 53
21
22
23
24
25
26, 27
28, 29
30
31, 32
33, 34
35
40
41, 42
43, 44
45
46
47, 48
Name
GND
FSEL_A0
FSEL_B0
FSEL_C0
FSEL_D0
FSEL_E0
V
DDA
Power
Input
Input
Input
Input
Input
Power
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Type
Description
Power supply ground.
Selects the QAx, nQAx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QBx, nQBx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QCx, nQCx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QDx, nQDx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QEx, nQEx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Analog supply pin.
nc
Unused
No connect.
XTAL_IN,
XTAL_OUT
REF_SEL
V
DD
PLL_SEL
CLK
nCLK
OE_A
V
DDO_A
QA0, nQA0
QA1, nQA1
OE_B
QB0, nQB0
QB1, nQB1
V
DDO_B
OE_C
QC0, nQC0
QC1, nQC1
V
DDO_C
V
DDO_D
QD0, nQD0
Input
Input
Power
Input
Input
Input
Input
Power
Output
Output
Input
Output
Output
Power
Input
Output
Output
Power
Power
Output
Pullup
Pullup
Pullup
Pulldown
Pullup/
Pulldown
Pullup
Pullup
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is
the input.
Input source control pin. See Table 3C. LVCMOS/LVTTL interface levels.
Core supply pins.
PLL bypass control pin. See Table 3B. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Active HIGH output enable for Bank A outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Bank A (HCSL) output supply pin. 3.3 V supply.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Active HIGH output enable for Bank B outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank B (HCSL) output supply pin. 3.3V supply.
Active HIGH output enable for Bank C outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank C (HCSL) output supply pin. 3.3V supply.
Bank D (HCSL) output and HCSL reference circuit supply pin. Must be
connected to 3.3V to use any of the HCSL outputs.
Differential output pair. HCSL interface levels.
©2016 Integrated Device Technology, Inc
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January 7, 2016
8413S12BI-126 Data Sheet
Table 1. Pin Descriptions
Number
49, 50
51
Name
QD1, nQD1
OE_D
Output
Input
Pullup
Type
Description
Differential output pair. HCSL interface levels.
Active HIGH output enable for Bank D outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
External fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode Q[Ax:Ex], nQ[Ax:EX]
outputs.
Bank E (HCSL) output supply pin. 3.3V supply.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Pullup
Active HIGH output enable for Bank E outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Active LOW Master Reset. When logic LOW, all outputs are reset causing
the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic HIGH, all outputs are enabled. LVCMOS/LVTTL interface
levels.
QF output supply pin (LVCMOS/LVTTL). 3.3V supply.
Single-ended output. 3.3V LVCMOS/LVTTL interface levels.
52
56
57, 58
59, 60
61
I
REF
V
DDO_E
QE0, nQE0
QE1, nQE1
OE_E
Input
Power
Output
Output
Input
62
nMR
Input
Pullup
63
64
V
DDO_F
QF
Power
Output
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
QF
V
DDO_F
= 3.465V
Test Conditions
CLK, nCLK
Control pins
Minimum
Typical
2
4
51
51
15
Maximum
Units
pF
pF
k
k
©2016 Integrated Device Technology, Inc
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January 7, 2016
8413S12BI-126 Data Sheet
Function Tables
Table 3A. FSEL_X Control Input Function Table
Input
FSEL_X[0]
0 (default)
1
Output Frequency
Q[Ax:Ex], nQ[Ax:Ex]
100MHz
156.25MHz
Table 3C. REF_SEL Control Input Function Table
Input
REF_SEL
0
1 (default)
Clock Source
CLK, nCLK
XTAL_IN, XTAL_OUT
NOTE: FSEL_X denotes FSEL_A, _B, _C, _D, _E.
NOTE Any two outputs operated at the same frequency will be
synchronous.
Table 3B. PLL_SEL Control Input Function Table
Input
PLL_SEL
0
1 (default)
Operation
PLL Bypass
PLL Mode
Table 3D. OE_[A:E] Control Input Function Table
Input
OE_[A:E]
0
1 (default)
Outputs
Q[Ax:Ex], nQ[Ax:Ex]
High-Impedance
Enabled
©2016 Integrated Device Technology, Inc
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January 7, 2016
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